Texas Instruments Datasheets for Flip-Flops
Flip-flops are digital logic devices that synchronize changes in output state (1 or 0) according to a clocked input.
Flip-Flops: Learn more
| Product Name | Notes |
|---|---|
| 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-SSOP -40 to 125 | |
| 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TSSOP -40 to 125 | |
| 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TSSOP | |
| 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TVSOP -40 to 125 | |
| 3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 48-SSOP -40 to 85 | |
| 3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 48-TSSOP -40 to 85 | |
| 3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 54-BGA MICROSTAR JUNIOR -40 to 85 | |
| 3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 56-BGA MICROSTAR JUNIOR -40 to 85 | |
| 3.3-V ABT 32-Bit Edge-Triggered D-Type Flip-Flop with 3-State Outputs 96-LFBGA -40 to 85 | |
| 4-Bit Bistable Latches 16-CDIP -55 to 125 | |
| 8-Bit Addressable Latches 20-LCCC -55 to 125 | |
| Automotive Catalog Dual Positive-Edge-Trigge red D-Type Flip-Flops with Set and Reset 14-SOIC -40 to 125 | |
| BiCMOS FCT Interface Logic Octal D-Type Flip-Flops with 3-State Outputs 20-PDIP 0 to 70 | |
| BiCMOS FCT Interface Logic Octal D-Type Flip-Flops with 3-State Outputs 20-SOIC 0 to 70 | |
| BiCMOS FCT Interface Logic Octal D-Type Flip-Flops with Reset 20-PDIP 0 to 70 | |
| BiCMOS FCT Interface Logic Octal D-Type Flip-Flops with Reset 20-SOIC 0 to 70 | |
| CMOS 4-Bit D-Type Registers with Clock and 3-State Outputs 16-CDIP -55 to 125 | |
| CMOS 4-Bit D-Type Registers with Clock and 3-State Outputs 16-PDIP -55 to 125 | |
| CMOS 4-Bit D-Type Registers with Clock and 3-State Outputs 16-SOIC -55 to 125 | |
| CMOS 4-Bit D-Type Registers with Clock and 3-State Outputs 16-TSSOP -55 to 125 | |
| CMOS Dual D-Type Flip Flop 14-CDIP -55 to 125 | |
| CMOS Dual D-Type Flip Flop 14-PDIP -55 to 125 | |
| CMOS Dual D-Type Flip Flop 14-SO -55 to 125 | |
| CMOS Dual D-Type Flip Flop 14-SOIC -55 to 125 | |
| CMOS Dual D-Type Flip Flop 14-TSSOP -55 to 125 | |
| CMOS Dual J-K Master-Slave Flip-Flop 16-CDIP -55 to 125 | |
| CMOS Dual J-K Master-Slave Flip-Flop 16-PDIP -55 to 125 | |
| CMOS Dual J-K Master-Slave Flip-Flop 16-SO -55 to 125 | |
| CMOS Dual J-K Master-Slave Flip-Flop 16-SOIC -55 to 125 | |
| CMOS Dual J-K Master-Slave Flip-Flop 16-TSSOP -55 to 125 | |
| CMOS Hex D-Type Flip-Flop 16-CDIP -55 to 125 | |
| CMOS Hex D-Type Flip-Flop 16-PDIP -55 to 125 | |
| CMOS Hex D-Type Flip-Flop 16-SO -55 to 125 | |
| CMOS Hex D-Type Flip-Flop 16-SOIC -55 to 125 | |
| CMOS Hex D-Type Flip-Flop 16-TSSOP -55 to 125 | |
| CMOS Quad D-Type Flip-Flop 16-CDIP -55 to 125 | |
| CMOS Quad D-Type Flip-Flop 16-PDIP -55 to 125 | |
| CMOS Quad D-Type Flip-Flop 16-SO -55 to 125 | |
| CMOS Quad D-Type Flip-Flop 16-SOIC -55 to 125 | |
| CMOS Quad D-Type Flip-Flop 16-TSSOP -55 to 125 | |
| CMOS Quad NAND R/S Latch with 3-State Outputs 16-CDIP -55 to 125 | |
| Dual D-type Positive-Edge-Trigge red Flip-Flops With Clear And Preset 14-CDIP -55 to 125 | |
| Dual D-type Positive-Edge-Trigge red Flip-Flops With Clear And Preset 14-CFP -55 to 125 | |
| Dual D-type Positive-Edge-Trigge red Flip-Flops With Clear And Preset 20-LCCC -55 to 125 | |
| Dual J-K Flip-Flops With Preset And Clear 16-CDIP -55 to 125 | |
| Dual J-K Negative-Edge-Trigge red Flip-Flops With Clear And Preset 16-CDIP -55 to 125 | |
| Dual J-K Negative-Edge-Trigge red Flip-Flops With Clear And Preset 16-CFP -55 to 125 | |
| Dual J-K Negative-Edge-Trigge red Flip-Flops With Clear And Preset 20-LCCC -55 to 125 | |
| Dual J-K Positive-Edge-Trigge red Flip-Flops With Clear And Preset 16-CDIP -55 to 125 | |
| Dual J-K Positive-Edge-Trigge red Flip-Flops With Clear And Preset 16-CFP -55 to 125 | |
| Dual J-K Positive-Edge-Trigge red Flip-Flops With Clear And Preset 20-LCCC -55 to 125 | |
| Dual Negative Edge Triggered J-K Flip-Flops with Set and Reset 16-CDIP -55 to 125 | |
| Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 | |
| Dual Negative-Edge-Trigge red J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | |
| Dual Negative-Edge-Trigge red J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 | |
| Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset 16-CDIP -55 to 125 | |
| Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | |
| Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 | |
| Dual Positive-Edge-Trigge red D-type Flip-Flops With Clear And Preset 14-CDIP -55 to 125 | |
| Dual Positive-Edge-Trigge red D-type Flip-Flops With Clear And Preset 14-CFP -55 to 125 | |
| Dual Positive-Edge-Trigge red D-type Flip-Flops With Clear And Preset 20-LCCC -55 to 125 | |
| Dual Positive-Edge-Trigge red D-Type Flip-Flops with Set and Reset 14-CDIP -55 to 125 | |
| Dual Positive-Edge-Trigge red D-Type Flip-Flops with Set and Reset 14-PDIP -55 to 125 | |
| Dual Positive-Edge-Trigge red D-Type Flip-Flops with Set and Reset 14-SOIC -55 to 125 | |
| Dual Positive-Edge-Trigge red J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | |
| Dual Positive-Edge-Trigge red J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 | |
| Hex D Flip-Flops with Reset 16-CDIP -55 to 125 | |
| Hex D-type Flip-Flops With Clear 16-CDIP -55 to 125 | |
| Hex D-type Flip-Flops With Clear 16-CFP -55 to 125 | |
| Hex D-type Flip-Flops With Clear 20-LCCC -55 to 125 | |
| Hex D-Type Flip-Flops with Reset 16-PDIP -55 to 125 | |
| Hex D-Type Flip-Flops with Reset 16-SOIC -55 to 125 | |
| High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch 16-CDIP -55 to 125 | |
| High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger 16-CDIP -55 to 125 | |
| High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125 | |
| High Speed CMOS Logic Dual Negative-Edge-Trigge red J-K Flip-Flops with Reset 14-PDIP -55 to 125 | |
| High Speed CMOS Logic Dual Negative-Edge-Trigge red J-K Flip-Flops with Reset 14-SOIC -55 to 125 | |
| High Speed CMOS Logic Dual Negative-Edge-Trigge red J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | |
| High Speed CMOS Logic Dual Negative-Edge-Trigge red J-K Flip-Flops with Set and Reset 16-SO -55 to 125 | |
| High Speed CMOS Logic Dual Negative-Edge-Trigge red J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 | |
| High Speed CMOS Logic Dual Negative-Edge-Trigge red J-K Flip-Flops with Set and Reset 16-TSSOP -55 to 125 | |
| High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset 14-CDIP -55 to 125 | |
| High Speed CMOS Logic Dual Positive-Edge Trigger J-K Flip-Flops with Set and Reset 16-CDIP -55 to 125 | |
| High Speed CMOS Logic Dual Positive-Edge-Trigge red J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | |
| High Speed CMOS Logic Dual Positive-Edge-Trigge red J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 | |
| High Speed CMOS Logic Hex D-Type Flip-Flops with Reset 16-CDIP -55 to 125 | |
| High Speed CMOS Logic Hex D-Type Flip-Flops with Reset 16-PDIP -55 to 125 | |
| High Speed CMOS Logic Hex D-Type Flip-Flops with Reset 16-SOIC -55 to 125 | |
| High Speed CMOS Logic Octal D-Type Flip-Flops with Data Enable 20-CDIP -55 to 125 | |
| High Speed CMOS Logic Octal D-Type Flip-Flops with Reset 20-CDIP -55 to 125 | |
| High Speed CMOS Logic Octal D-Type Positive-Edge Triggered Inverting Flip-Flops with 3-State Outputs 20-CDIP -55 to 125 | |
| High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State Output 20-CDIP -55 to 125 | |
| High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State Outputs 20-CDIP -55 to 125 | |
| High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs 16-CDIP -55 to 125 | |
| High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs 16-PDIP -55 to 125 | |
| High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs 16-SOIC -55 to 125 | |
| High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs 16-TSSOP -55 to 125 | |
| High Speed CMOS Logic Quad D-Type Flip-Flops with Reset 16-CDIP -55 to 125 | |
| Non-Inverting Octal D-Type Flip-Flops with 3-State Outputs 20-CDIP -55 to 125 | |
| Octal 4-Bit D-type Edge-Triggered Flip-Flops with 3-state Outputs 24-CDIP -55 to 125 | |
| Octal 4-Bit D-type Edge-Triggered Flip-Flops with 3-state Outputs 28-LCCC -55 to 125 | |
| Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-CDIP -55 to 125 | |
| Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-CFP -55 to 125 | |
| Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-LCCC -55 to 125 | |
| Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-CDIP -55 to 125 | |
| Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-CFP -55 to 125 | |
| Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-LCCC -55 to 125 | |
| Octal D-type Flip-Flop With Clear 20-CDIP -55 to 125 | |
| Octal D-type Flip-Flop With Clear 20-CFP -55 to 125 | |
| Octal D-type Flip-Flop With Clear 20-LCCC -55 to 125 | |
| Octal D-Type Flip-Flops with 3-State Outputs 20-CDIP -55 to 125 | |
| Octal D-Type Flip-Flops with 3-State Outputs 20-PDIP -55 to 125 | |
| Octal D-Type Flip-Flops with 3-State Outputs 20-SOIC -55 to 125 | |
| Octal D-type Flip-Flops With Clear 20-CDIP -55 to 125 | |
| Octal D-type Flip-Flops With Clear 20-CFP -55 to 125 | |
| Octal D-type Flip-Flops With Clear 20-LCCC -55 to 125 | |
| Octal D-Type Flip-Flops with Reset 20-CDIP -55 to 125 | |
| Octal D-Type Flip-Flops with Reset 20-PDIP -55 to 125 | |
| Octal D-Type Flip-Flops with Reset 20-SOIC -55 to 125 | |
| Octal D-Type Flip-Flops with Reset 20-SSOP -55 to 125 | |
| Octal D-Type Flip-Flops with Reset 20-TSSOP -55 to 125 | |
| Octal D-Type Transparent Latches with 3-state Outputs 20-CFP -55 to 125 | |
| Octal Non-Inverting D-Type Flip-Flops with 3-State Outputs 20-PDIP -55 to 125 | |
| Octal Non-Inverting D-Type Flip-Flops with 3-State Outputs 20-SOIC -55 to 125 | |
| Quad D-Type Flip-Flops with Reset 16-PDIP -55 to 125 | |
| Quad D-Type Flip-Flops with Reset 16-SOIC -55 to 125 | |
| Quadruple /S-/R Latches 16-CFP -55 to 125 | |
| Quadruple D-type Flip-Flops With Clear 16-CDIP -55 to 125 | |
| Quadruple D-type Flip-Flops With Clear 16-CFP -55 to 125 | |
| Quadruple D-type Flip-Flops With Clear 20-LCCC -55 to 125 | |
| Single D-Type Flip-Flop with 3-State Output 6-SC70 -40 to 125 | |
| Single D-Type Flip-Flop with Asynchronous Clear 6-SC70 -40 to 125 | |
| Single D-Type Flip-Flop with Asynchronous Clear 6-SOT-23 -40 to 125 | |
| Single D-Type Latch with 3S Output 6-SOT-23 -40 to 125 |
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