Texas Instruments Datasheets for Flip-Flops
Flip-flops are digital logic devices that synchronize changes in output state (1 or 0) according to a clocked input.
Flip-Flops: Learn more
| Product Name | Notes |
|---|---|
| 10-Bit Bus Interface Flip-Flops With 3-State Outputs 24-CDIP -55 to 125 | |
| 10-Bit Bus Interface Flip-Flops With 3-State Outputs 24-CFP -55 to 125 | |
| 10-Bit Bus Interface Flip-Flops With 3-State Outputs 28-LCCC -55 to 125 | |
| 16-Bit D-type Edge-Triggered Flip-Flops With 3-State Outputs 48-CFP -55 to 125 | |
| 16-Bit D-Type Edge-Triggered Flip-Flops With 3-State Outputs 48-SSOP -40 to 85 | |
| 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-SSOP -40 to 85 | |
| 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TSSOP -40 to 85 | |
| 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TVSOP -40 to 85 | |
| 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 56-BGA MICROSTAR JUNIOR -40 to 85 | |
| 16-Bit Edge-Triggered D-Type Flip-Flops with 3-State Output 48-SSOP -40 to 85 | |
| 16-Bit Edge-Triggered D-Type Flip-Flops with 3-State Output 48-TSSOP -40 to 85 | |
| 16-Bit Edge-Triggered D-type Flip-Flops With 3-State Outputs 48-CFP -55 to 125 | |
| 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 48-SSOP -40 to 85 | |
| 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 48-TSSOP -40 to 85 | |
| 16-Bit Transparent D-Type Latch With 3-State Outputs 56-BGA MICROSTAR JUNIOR -40 to 85 | |
| 18-Bit Bus-Interface Flip-Flops with 3-State Outputs 56-SSOP -40 to 85 | |
| 18-Bit Bus-Interface Flip-Flops With 3-State Outputs 56-TSSOP -40 to 85 | |
| 18-Bit D-Type Flip-Flops with 3-State Outputs 56-SSOP -40 to 85 | |
| 18-Bit D-Type Flip-Flops with 3-State Outputs 56-TSSOP -40 to 85 | |
| 2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 56-BGA MICROSTAR JUNIOR -40 to 85 | |
| 2.5-V/3.3-V 32-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 96-LFBGA -40 to 85 | |
| 22-Bit Flip-Flop With 3-State Outputs 64-TSSOP -40 to 85 | |
| 3.3-V 20-Bit Flip-Flop With 3-State Outputs 56-TSSOP -40 to 85 | |
| 3.3-V ABT 16-Bit Edge-Triggered D-type Flip-Flops With 3-State Outputs 48-CFP -55 to 125 | |
| 3.3-V ABT Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-CDIP -55 to 125 | |
| 3.3-V ABT Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-CFP -55 to 125 | |
| 3.3-V ABT Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-LCCC -55 to 125 | |
| 32-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 96-LFBGA -40 to 85 | |
| 8-Bit Addressable Latches 16-CDIP -55 to 125 | |
| 8-Bit Bus-Interface Flip-Flops With 3-State Outputs 24-CDIP -55 to 125 | |
| 8-Bit Bus-Interface Flip-Flops With 3-State Outputs 24-CFP -55 to 125 | |
| 8-Bit Bus-Interface Flip-Flops With 3-State Outputs 28-LCCC -55 to 125 | |
| 9-Bit Bus Interface Flip-Flops With 3-State Outputs 24-CDIP -55 to 125 | |
| 9-Bit Bus Interface Flip-Flops With 3-State Outputs 24-CFP -55 to 125 | |
| 9-Bit Bus Interface Flip-Flops With 3-State Outputs 28-LCCC -55 to 125 | |
| 9-Bit Bus-Interface Flip-Flops With 3-State Outputs 24-CDIP -55 to 125 | |
| 9-Bit Bus-Interface Flip-Flops With 3-State Outputs 24-CFP -55 to 125 | |
| 9-Bit Bus-Interface Flip-Flops With 3-State Outputs 28-LCCC -55 to 125 | |
| Dual D-type Positive-Edge-Trigge red Flip-Flops With Clear And Preset 14-CDIP -55 to 125 | |
| Dual D-type Positive-Edge-Trigge red Flip-Flops With Clear And Preset 14-CFP -55 to 125 | |
| Dual J-K Flip-Flops With Clear and 3-state Outputs 14-CDIP -55 to 125 | |
| Dual J-K Flip-Flops With Clear and 3-state Outputs 14-CFP -55 to 125 | |
| Dual J-K Flip-Flops With Preset And Clear 16-CDIP -55 to 125 | |
| Dual J-K Flip-Flops With Preset And Clear 16-CFP -55 to 125 | |
| Dual J-K Positive-Edge-Trigge red Flip-Flops W/Clear And Preset 16-CDIP -55 to 125 | |
| Dual J-K Positive-Edge-Trigge red Flip-Flops W/Clear And Preset 16-CFP -55 to 125 | |
| Dual J-K Positive-Edge-Trigge red Flip-Flops W/Clear And Preset 20-LCCC -55 to 125 | |
| Dual J-K Positive-Edge-Trigge red Flip-Flops With Clear And Preset 16-CDIP | |
| Dual J-K Positive-Edge-Trigge red Flip-Flops With Clear And Preset 16-CFP | |
| Dual Positive-Edge-Trigge red D-type Flip-Flops With Clear And Preset 14-CDIP -55 to 125 | |
| Dual Positive-Edge-Trigge red D-type Flip-Flops With Clear And Preset 14-CFP -55 to 125 | |
| Dual Positive-Edge-Trigge red D-Type Flip-Flops With Clear and Preset 14-PDIP -40 to 85 | |
| Dual Positive-Edge-Trigge red D-Type Flip-Flops With Clear and Preset 14-SO -40 to 85 | |
| Dual Positive-Edge-Trigge red D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 85 | |
| Dual Positive-Edge-Trigge red D-Type Flip-Flops With Clear and Preset 14-SSOP -40 to 85 | |
| Dual Positive-Edge-Trigge red D-Type Flip-Flops With Clear and Preset 14-TSSOP -40 to 85 | |
| Dual Positive-Edge-Trigge red D-type Flip-Flops With Clear And Preset 20-LCCC -55 to 125 | |
| Dual Positive-Edge-Trigge red D-Type- Flip-Flops With Clear And Preset 14-CDIP -55 to 125 | |
| Dual Positive-Edge-Trigge red D-Type- Flip-Flops With Clear And Preset 14-CFP -55 to 125 | |
| Dual Positive-Edge-Trigge red D-Type- Flip-Flops With Clear And Preset 20-LCCC -55 to 125 | |
| Hex D-type Flip-Flops With Enable 16-CDIP -55 to 125 | |
| Hex D-type Flip-Flops With Enable 16-CFP -55 to 125 | |
| Hex/Quadruple D-type Flip-Flops With Clear 16-CDIP -55 to 125 | |
| Hex/Quadruple D-type Flip-Flops With Clear 20-LCCC -55 to 125 | |
| High Speed CMOS Logic 8-Bit Addressable Latch 16-CDIP -55 to 125 | |
| High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger 16-CDIP -55 to 125 | |
| High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125 | |
| High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset 14-CDIP -55 to 125 | |
| High Speed CMOS Logic Dual Positive-Edge Trigger J-K Flip-Flops with Set and Reset 16-CDIP -55 to 125 | |
| High Speed CMOS Logic Hex D-Type Flip-Flops with Reset 16-CDIP -55 to 125 | |
| High Speed CMOS Logic Octal D-Type Flip-Flops with Data Enable 20-CDIP -55 to 125 | |
| High Speed CMOS Logic Octal D-Type Flip-Flops with Reset 20-CDIP -55 to 125 | |
| High Speed CMOS Logic Octal D-Type Positive-Edge Triggered Inverting Flip-Flops with 3-State Outputs 20-CDIP -55 to 125 | |
| High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State Outputs 20-CDIP -55 to 125 | |
| High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs 16-CDIP -55 to 125 | |
| High Speed CMOS Logic Quad D-Type Flip-Flops with Reset 16-CDIP -55 to 125 | |
| Octal D-type Edge Triggered Flip-Flops with 3-state Outputs 20-CDIP -55 to 125 | |
| Octal D-type Edge Triggered Flip-Flops with 3-state Outputs 20-CFP -55 to 125 | |
| Octal D-type Edge Triggered Flip-Flops with 3-state Outputs 20-LCCC -55 to 125 | |
| Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs 20-CDIP -55 to 125 | |
| Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs 20-CFP -55 to 125 | |
| Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs 20-LCCC -55 to 125 | |
| Octal D-type Flip-Flop With Clear 20-CDIP -55 to 125 | |
| Octal D-type Flip-Flop With Clear 20-CFP -55 to 125 | |
| Octal D-Type Flip-Flops with Clear 20-CDIP -55 to 125 | |
| Octal D-type Flip-Flops With Clear 20-CDIP | |
| Octal D-type Flip-Flops With Clear 20-CFP -55 to 125 | |
| Octal D-type Flip-Flops With Clear 20-CFP | |
| Octal D-Type Flip-Flops with Clear 20-LCCC -55 to 125 | |
| Octal D-Type Flip-Flops with Enable 20-LCCC -55 to 125 | |
| Octal D-Type Registers with 3-State Outputs 20-CDIP -55 to 125 | |
| Octal D-Type Registers with 3-State Outputs 20-LCCC -55 to 125 | |
| Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-CDIP -55 to 125 | |
| Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-CFP -55 to 125 | |
| Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-LCCC -55 to 125 | |
| Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 24-PDIP -40 to 85 | |
| Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 24-SOIC -40 to 85 | |
| Octal Edge-Triggered D-type Flip-Flops With Clear 20-CDIP -55 to 125 | |
| Octal Edge-Triggered D-type Flip-Flops With Clear 20-CFP -55 to 125 | |
| Octal Edge-Triggered D-type Flip-Flops With Clear 20-LCCC -55 to 125 | |
| Octal Edge-Triggered D-type Flip-Flops With Clock Enable 20-CDIP -55 to 125 | |
| Octal Edge-Triggered D-type Flip-Flops With Clock Enable 20-CFP -55 to 125 | |
| Octal Edge-Triggered D-type Flip-Flops With Clock Enable 20-LCCC -55 to 125 | |
| Octal, Hex, And Quad D-type Flip-Flops With Clock Enable 20-CDIP -55 to 125 | |
| Octal, Hex, And Quad D-type Flip-Flops With Clock Enable 20-LCCC -55 to 125 | |
| Scan Test Devices With Octal D-type Edge-Triggered Flip-Flops 24-CDIP -55 to 125 | |
| Scan Test Devices With Octal D-type Edge-Triggered Flip-Flops 28-LCCC -55 to 125 |
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