Texas Instruments Datasheets for Logic Level Translators
Logic level translators adapt or convert one voltage or logic level to another.
Logic Level Translators: Learn more
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| Product Name | Notes |
|---|---|
| 10-Bit Voltage Clamp 24-TSSOP -40 to 85 | |
| 12-Bit GTL-/GTL/GTL+ to LVTTL Translator 28-TSSOP -40 to 85 | |
| 16-Bit LVTTL To GTL/GTL+ Universal Bus Transceivers with Live Insertion 64-TSSOP -40 to 85 | |
| 16-Bit LVTTL-to-GTLP Adjustable-Edge-Rate Bus Transceiver 56-TSSOP -40 to 85 | |
| 16-Bit LVTTL-to-GTLP Adjustable-Edge-Rate Bus Transceiver 56-TVSOP -40 to 85 | |
| 17-Bit LVTTL-To-GTL/GTL+ Universal Bus Transceivers With Buffered Clock Outputs 56-SSOP -40 to 85 | |
| 17-Bit LVTTL-To-GTL/GTL+ Universal Bus Transceivers With Buffered Clock Outputs 56-TSSOP -40 to 85 | |
| 17-Bit LVTTL/BTL Universal Storage Transceivers With Buffered Clock Lines 100-HLQFP 0 to 70 | |
| 18-Bit GTL/LVT Universal Bus Transceivers 56-CFP -55 to 125 | |
| 18-Bit LVTTL To GTL/GTL+ Bus Transceiver 64-TSSOP -40 to 85 | |
| 18-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceivers 56-SSOP -40 to 85 | |
| 18-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceivers 56-TSSOP -40 to 85 | |
| 18-Bit TTL/BTL Universal Storage Transceiver 100-HLQFP 0 to 70 | |
| 2-Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvr w/Split LVTTL Port, Feedback Path, & Selectable Polarity 16-SOIC -40 to 85 | |
| 2-Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvr w/Split LVTTL Port, Feedback Path, & Selectable Polarity 16-TSSOP -40 to 85 | |
| 4-bits LVTTL to GTL Transceiver 14-TSSOP -40 to 85 | |
| 8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver with Split LVTTL Port and Feedback Path 48-TSSOP -40 to 85 | |
| 8-Bit LVTTL-to-GTLP Bus Transceiver 24-TVSOP -40 to 85 | |
| 8-Bit TTL/BTL Registered Transceiver 52-QFP 0 to 70 | |
| 8-Bit TTL/BTL Transceivers 52-QFP 0 to 70 | |
| 9-Bit TTL/BTL Address/Data Transceiver 52-QFP 0 to 70 | |
| Octal ECL-to-TTL Translator With 3-State Outputs 24-PDIP 0 to 70 | |
| Octal ECL-to-TTL Translator With 3-State Outputs 24-SOIC 0 to 70 | |
| Octal ECL-to-TTL Translator With D-Type Edge-Triggered Flip-Flops and 3-State Outputs 24-SOIC 0 to 70 | |
| Octal TTL-to-ECL Translators With Output Enable 24-SOIC 0 to 70 | |
| Selectable GTL Voltage Reference 6-SC70 -40 to 85 | |
| Two 1-Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-SOIC -40 to 85 | |
| Two 1-Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-TSSOP -40 to 85 |
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