Integrated Device Technology Datasheets for Memory Chips
Memory chips are internal storage areas in computers. Although the term "memory chip" commonly refers to a computer's random access memory (RAM), this product area includes many different types of electronic data storage. Computer memory stores data electronically in cells. Without memory chips, a computer could not read programs or retain data.
Memory Chips: Learn more
| Product Name | Notes |
|---|---|
| The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of... | |
| The 71V3578 3.3V CMOS SRAM is organized as 256K x 18. The 71V3578 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of... | |
| The 71V3579 3.3V CMOS SRAM is organized as 256K x 18. The 71V3579 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of... | |
| The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL -compatible and operation is from a single 3.3V supply. | |
| The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL -compatible and operation is from a single 3.3V supply. | |
| The 71V546 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or... | |
| The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or... | |
| The 71V632 3.3V CMOS SRAM is organized as 64K x 32. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz. The 71V632 SRAM contains... | |
| The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes... | |
| The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes... | |
| The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and... | |
| The 71V65903 3.3V CMOS SRAM is organized as 512K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes... | |
| The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed... | |
| The 71V67603 3.3V CMOS SRAM is organized as 256K x 36. The 71V67603 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of... | |
| The 71V67703 3.3V CMOS SRAM is organized as 256K x 36. The 71V67703 SRAM contains write, data, address and control registers. There are no registers in the data output path... | |
| The 71V67803 3.3V CMOS SRAM is organized as 512K x 18. The 71V67803 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of... | |
| The 71V67903 3.3V CMOS SRAM is organized as 512K x 18. The 71V67903 SRAM contains write, data, address and control registers. There are no registers in the data output path... | |
| The 7200 is a 256 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow... | |
| The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow... | |
| The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow... | |
| The 7203 is a 2K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow... | |
| The 7204 is a 4K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow... | |
| The 7205 is a 8K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow... | |
| The 7206 is a 16K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow... | |
| The 7207 is a 32K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow... | |
| The 7208 is a 64K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow... | |
| The 72125 is a 1K x 16 dedicated, parallel-to-serial FIFOs. The ability to buffer wide word widths (x16) make this FIFO ideal for laser printers, FAX machines, local area networks... | |
| The 72201SyncFIFO™ is a 256 x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as... |
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