The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM , or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM .
SRAM - Synchronous, SDR (ZBT) Memory IC 9Mbit Parallel 133 MHz 4.2 ns 165-CABGA (13x15)
IC SRAM 9MBIT PARALLEL 165CABGA
| Integrated Device Technology | Quarktwin Technology Ltd. | Shenzhen Shengyu Electronics Technology Limited | |
|---|---|---|---|
| Product Category | Memory Chips | Memory Chips | Memory Chips |
| Product Number | 71V65803S133BQI | 71V65803S133BQI | 71V65803S133BQI |
| Product Name | 3.3V 512K x 18 ZBT Synchronous 3.3V I/O PipeLined SRAM | Memory | Integrated Circuits (ICs) - Memory |
| Memory Category | SRAM Chip | SRAM; SRAM Chip | Volatile; SRAM Chip |
| Data Rate | 133 MHz | 133 MHz | |
| Operating Temperature | -40 to 85 C (-40 to 185 F) | -40 to 85 C (-40 to 185 F) | -40 to 85 C (-40 to 185 F) |
| Density | 512 kbits | 9000 kbits | 9000 kbits |
| Number of Words | 512 k |
