The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM , or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM .
SRAM - Synchronous, SDR (ZBT) Memory IC 9Mbit Parallel 8.5 ns 165-CABGA (13x15)
IC SRAM 9MBIT PARALLEL 165CABGA
| Integrated Device Technology | Quarktwin Technology Ltd. | Shenzhen Shengyu Electronics Technology Limited | |
|---|---|---|---|
| Product Category | Memory Chips | Memory Chips | Memory Chips |
| Product Number | 71V65703S85BQI | 71V65703S85BQI | 71V65703S85BQI |
| Product Name | 3.3V 256K x 36 ZBT Synchronous 3.3V I/O Flowthrough SRAM | Memory | Integrated Circuits (ICs) - Memory - Memory |
| Memory Category | SRAM Chip | SRAM; SRAM Chip | Volatile; SRAM Chip |
| Cycle Time | 85 ns | 8.5 ns | |
| Operating Temperature | -40 to 85 C (-40 to 185 F) | -40 to 85 C (-40 to 185 F) | |
| Density | 256 kbits | 9000 kbits | 9000 kbits |
| Number of Words | 256 k |
