Integrated Device Technology 3.3V 256K x 36 Synchronous 2.5V I/O PipeLined SRAM 71V67602S150BGG8

Description
The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM .
Datasheet
Description
The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM .
Datasheet

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3.3V 256K x 36 Synchronous 2.5V I/O PipeLined SRAM - 71V67602S150BGG8 - Integrated Device Technology
San Jose, CA, USA
3.3V 256K x 36 Synchronous 2.5V I/O PipeLined SRAM
71V67602S150BGG8
3.3V 256K x 36 Synchronous 2.5V I/O PipeLined SRAM 71V67602S150BGG8
The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM .

The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM .

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Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 71V67602S150BGG8
Product Name 3.3V 256K x 36 Synchronous 2.5V I/O PipeLined SRAM
Memory Category SRAM Chip
Data Rate 150 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 256 kbits
Number of Words 256 k
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