Integrated Device Technology Datasheets for IC Interfaces
IC interfaces are semiconductor chips that are used to control and manage the sharing of information between devices.
IC Interfaces: Learn more
| Product Name | Notes |
|---|---|
| 2.5V Zero Delay Clock Buffer, Spread Spectrum Compatible | |
| 3.3V Zero Delay Clock Buffer, Spread Spectrum Compatible | |
| Alternative Products NOTICE - The following device(s) are recommended alternatives: 524S - Low Skew 1 to 4 Clock Buffer Improved jitter performance, smaller package The 524 is a low skew,... | |
| Alternative Products NOTICE - The following device(s) are recommended alternatives: 551S - Low Skew 1 to 4 Clock Buffer Improved jitter performance, smaller package, 1.8V to 3.3V supply voltage The... | |
| Alternative Products NOTICE - The following device(s) are recommended alternatives: 553S - Low Skew 1 to 4 Clock Buffer Improved jitter performance, smaller package, 1.8V to 3.3V supply voltage The... | |
| SOIC 150 MIL | |
| The 2304NZ -1 is a high-performance, low skew, low jitter PCI / PCI -X clock driver. It is designed to distribute high-speed signals in PCI / PCI -X applications operating... | |
| The 2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on IDT 's proprietary low jitter Phase Locked Loop ( PLL ) techniques, the device... | |
| The 2305A is a high-speed phase-lock loop ( PLL ) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the... | |
| The 2305B is a high-speed phase-lock loop ( PLL ) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the... | |
| The 2308 is a high-speed phase-lock loop ( PLL ) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning... | |
| The 2308A is a high-speed phase-lock loop ( PLL ) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning... | |
| The 2308B is a high-speed phase-lock loop ( PLL ) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning... | |
| The 2309 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on ICS ' proprietary low jitter Phase Locked Loop ( PLL ) techniques, the device... | |
| The 2309A is a high-speed phase-lock loop ( PLL ) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the... | |
| The 2402 is a high-performance Zero Delay Buffer ( ZDB ) which integrates IDT 's proprietary analog/digital Phase-Locked Loop ( PLL ) techniques. The chip is part of IDT 's... | |
| The 49FCT805 is a non-inverting buffer/clock driver built using advanced dual metal CMOS technology. Each bank consists of two banks of drivers. Each bank drives five output buffers from a... | |
| The 4DB0124K is a DDR4 Data Buffer with a dual 4-bit bidirectional data register with differential strobes is designed for 1.2 VDD operation. | |
| The 501 Loco™ is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for Low... | |
| The 501A is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. It is designed to replace... | |
| The 501B Loco™ is the most cost effective way to generate a high-quality clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost... | |
| The 502 Loco™ is the most cost effective way to generate a high-quality, high-frequency clock output and a reference from a lower frequency crystal or clock input. The name LOCO... | |
| The 508 is the most cost effective way to generate a high quality, high frequency CMOS clock output from a PECL clock input. The 508 has separate VDD supplies for... | |
| The 511 Loco™ is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands... | |
| The 524S is a low skew, single input to four output, LVCMOS clock buffer. The 524S has best in class additive phase Jitter of sub 50 fsec. | |
| The 527-01 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce... | |
| The 542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V... | |
| The 54FCT162244T 16-Bit high speed and low power Buffer/Line Driver is for bus interface or signal buffering applications and has three-state controls allowing independent 4-bit, 8-bit or combined 16-bit operation. | |
| The 54FCT162245T 16-bit high-speed, low-power transceiver is ideal for synchronous communication between two buses and can operate as either two independent 8-bit transceivers or one 16-bit transceiver. The 54FCT162245T operates... | |
| The 54FCT16244T 16-Bit high speed and low power Buffer/Line Driver has three-state controls allowing independent 4-bit, 8-bit or combined 16-bit operation. It is ideally suited for driving high capacitance loads(>200pF)... | |
| The 54FCT16245T 16-bit high-speed, low-power transceiver is ideal for synchronous communication between two buses. The Direction and Output Enable controls operate these devices as either two independent 8-bit transceivers or... | |
| The 54FCT244T octal buffer/line driver is designed to be employed as a memory and address driver, clock driver, and bus-oriented transmitter/receiver which provides improved board density. The 54FCT244T operates at... | |
| The 54FCT245T octal bidirectional transceiver is designed for asynchronous two way communication between data buses. The transmit/receive (T/R) input determines the direction of data flow through the bidirectional transceiver. The... | |
| The 551S is a low cost, high-speed single input to four output LVCMOS clock buffer. The 551S has best in class Additive Phase Jitter of sub 50 fsec. | |
| The 552-02 is a low skew, single-input to eightoutput clock buffer. The device offers a dual input with pin select for switching between two clock sources. It is part of... | |
| The 552A-01 produces 8 low-skew copies of the multiple input clock or fundamental, parallel-mode crystal. Unlike other clock drivers, these parts do not require a separate oscillator for the input. | |
| The 553S is a low skew, single input to four output, LVCMOS clock buffer. The 553S has best in class additive phase Jitter of sub 50 fsec. | |
| The 557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) input pairs and fans out to one pair... | |
| The 558-01 accepts a high speed input of either PECL or CMOS , integrates a divider of 1, 2, 3, or 4, and provides four CMOS low skew outputs. The... | |
| The 571 is a high speed, high output drive, low phase noise Zero Delay Buffer ( ZDB ) which integrates IDT 's proprietary analog/digital Phase Locked Loop ( PLL )... | |
| The 574 is a low jitter, low-skew, high performance PLL -based zero delay buffer for high speed applications. Based on IDT 's proprietary low jitter Phase Locked Loop ( PLL... | |
| The 580-01 is a clock multiplexer (mux) designed to switch between two clock sources with no glitches or short pulses. The operation of the mux is controlled by an input... | |
| The 5962-92203 (equivalent to IDT 54FCT244T ) octal buffer/line driver is designed to be employed as a memory and address driver, clock driver, and bus-oriented transmitter/receiver which provides improved board... | |
| The 5962-92213 (equivalent to IDT 54FCT240T ) octal buffer/line driver is designed to be employed as a memory and address driver, clock driver, and bus-oriented transmitter/ receiver which provides improved... | |
| The 5962-92214 (equivalent to IDT 54FCT245T ) octal bidirectional transceiver is designed for asynchronous two way communication between data buses. The transmit/receive (T/R) input determines the direction of data flow... | |
| The 5962-92257 (equivalent to IDT 54FCT16244T ) 16-Bit high speed and low power Buffer/Line Driver has three-state controls allowing independent 4-bit, 8-bit or combined 16-bit operation. It is ideally suited... | |
| The 5962-92258 (equivalent to IDT 54FCT16245T ) 16-bit high-speed, low-power transceiver is ideal for synchronous communication between two buses. The Direction and Output Enable controls operate these devices as either... | |
| The 5962-92271 (equivalent to IDT 54FCT162244T ) 16-Bit high speed and low power Buffer/Line Driver is for bus interface or signal buffering applications and has three-state controls allowing independent 4-bit,... | |
| The 5962-92272 (equivalent to 54FCT162245T ) 16-bit high-speed, low-power transceiver is ideal for synchronous communication between two buses and can operate as either two independent 8-bit transceivers or one 16-bit... | |
| The 5P1103 is a programmable fanout buffer intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable ( OTP ) memory... | |
| The 5P1105 is a programmable fanout buffer intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable ( OTP ) memory... | |
| The 5PB1102 is a high-performance 1:2 LVCMOS clock buffer. It has best-in-class Additive Phase Jitter of 50fsec RMS . The 5PB1102 also supports an Output Enable function. It is available... | |
| The 5PB1104 is a high-performance 1:4 LVCMOS clock buffer. It has best-in-class Additive Phase Jitter of 50 fsec RMS . The 5PB1104 also supports an Output Enable function. It is... | |
| The 5PB1106 is a high-performance 1:6 LVCMOS clock buffer. It has best-in-class Additive Phase Jitter of 50 fsec RMS . The 5PB1106 also supports an Output Enable function. It is... | |
| The 5PB1108 is a high-performance 1:8 LVCMOS clock buffer. It has best-in-class Additive Phase Jitter of 50 fsec RMS . The 5PB1108 also supports an Output Enable function. It is... | |
| The 5PB1110 is a high-performance 1:10 LVCMOS clock buffer. It has best-in-class Additive Phase Jitter of 50 fsec RMS . The 5PB1110 also supports an Output Enable function. It is... | |
| The 5T9304 differential clock buffer has a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver... | |
| The 5T9304I differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver... | |
| The 5T9306 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding... | |
| The 601-02 is a low cost, low phase noise, high performance clock synthesizer for any application that requires low phase noise and low jitter. The 601 is IDT ’s lowest... | |
| The 621 is a low skew, single input to four output, clock buffer. The device operates from a single 1.2 to 1.8 volt supply and has a 3.3 volt tolerant... | |
| The FCT3805 is a 3.3 volt clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output... | |
| The FCT3805 is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and... | |
| The FCT3805B is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and... | |
| The FCT806 is an inverting buffer/clock driver built using advanced dual metal CMOS technology. Each bank consists of two banks of drivers. Each bank drives five output buffers from a... | |
| The ICS601 -01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT ’s lowest phase noise multiplier,... | |
| The IDT 4DB0226K is a JEDEC compliant DDR4 data butter for Enterprise Class Server LRDIMMs operating with a 1.2V Vdd supply. Nine data buffers are used per LRDIMM to buffer... | |
| The IDT 54FCT240T octal buffer/line driver is designed to be employed as a memory and address driver, clock driver, and bus-oriented transmitter/ receiver which provides improved board density. The 5962-92213... | |
| The IDT2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on the IDT proprietary low jitter Phase Locked Loop ( PLL ) techniques, the device... | |
| The IDT2305NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems. The IDT2305NZ operates at 3.3V with five outputs that can run... | |
| The IDT2308 is a high-speed phase-lock loop ( PLL ) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning... | |
| The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which... | |
| The IDT23S09 is a high-speed phase-lock loop ( PLL ) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the... | |
| The IDT512 is the most cost effective way to generate a high quality, high frequency clock output and a reference clock from a lower frequency crystal or clock input, and... | |
| The IDT570 is a high-performance Zero Delay Buffer ( ZDB ) which integrates IDT 's proprietary analog/digital Phase Locked Loop ( PLL ) techniques. The A version is recommended for... | |
| The IDT5P61006 is a low-cost, low voltage zero delay buffer for DDR2 /800 applications. Using analog/digital Phase-Locked Loop techniques, the device accepts a 425 MHz clock input and provides a... | |
| The IDT5T30553 is a low skew, single input to four output, clock buffer. IDT makes many non- PLL and PLL based low skew output devices as well as Zero Delay... | |
| The IDT5V2305 is a high performance, low skew clock buffer that operates up to 200MHz. One bank of five outputs provides low skew copies of CLK . Through the use... | |
| The IDT5V2310 is a high performance, low skew clock buffer that operates up to 200MHz. Two banks of five outputs each provide low skewcopies of CLK . Through the use... | |
| This buffer/clock driver is built using advanced dual metal CMOS technology. The FCT805T is a non-inverting clock driver consisting of two banks of drivers. Each bank drives five output buffers... | |
| TSSOP 4.4 MM 0.65MM PITCH |
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