The 71V546 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM , or Zero Bus Turn-around. The 71V546 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM .
IC SRAM 4.5MBIT PARALLEL 100TQFP
SRAM - Synchronous, SDR (ZBT) Memory IC 4.5Mbit Parallel 133 MHz 4.2 ns 100-TQFP (14x14)
| Integrated Device Technology | Shenzhen Shengyu Electronics Technology Limited | Quarktwin Technology Ltd. | |
|---|---|---|---|
| Product Category | Memory Chips | Memory Chips | Memory Chips |
| Product Number | 71V546S133PFG | 71V546S133PFG | 71V546S133PFG |
| Product Name | 3.3V 128K x 36 ZBT Synchronous PipeLined SRAM | Integrated Circuits (ICs) - Memory - Memory | Memory |
| Memory Category | SRAM Chip | Volatile; SRAM Chip | SRAM; SRAM Chip |
| Data Rate | 133 MHz | 133 MHz | |
| Operating Temperature | 0 to 70 C (32 to 158 F) | 0 to 70 C (32 to 158 F) | |
| Density | 128 kbits | 4500 kbits | 4500 kbits |
| Number of Words | 128 k |
