Integrated Device Technology 512 x 9 AsyncFIFO, 5.0V 7201LA12SOG8

Description
The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit ( RT ) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW . It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
Datasheet
Description
The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit ( RT ) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW . It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
Datasheet

Suppliers

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512 x 9 AsyncFIFO, 5.0V - 7201LA12SOG8 - Integrated Device Technology
San Jose, CA, USA
512 x 9 AsyncFIFO, 5.0V
7201LA12SOG8
512 x 9 AsyncFIFO, 5.0V 7201LA12SOG8
The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit ( RT ) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW . It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit ( RT ) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW . It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

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Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 7201LA12SOG8
Product Name 512 x 9 AsyncFIFO, 5.0V
Memory Category FIFO
Logic Family TTL
Access Time 12 ns
Operating Temperature 0 to 70 C (32 to 158 F)
Density 4 kbits
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