Integrated Device Technology Datasheets for Memory Chips
Memory chips are internal storage areas in computers. Although the term "memory chip" commonly refers to a computer's random access memory (RAM), this product area includes many different types of electronic data storage. Computer memory stores data electronically in cells. Without memory chips, a computer could not read programs or retain data.
Memory Chips: Learn more
| Product Name | Notes |
|---|---|
| The 7134 is a high-speed 4K x 8 Dual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to... | |
| The 7140 is a high-speed 1K x 8 Dual-Port Static RAM designed to be used as a “ SLAVE ” Dual-Port RAM together with the 7130 “ MASTER ” Dual-Port... | |
| The 7142 is a high-speed 2K x 8 Dual-Port Static RAM designed to be used as a “ SLAVE ” Dual-Port RAM together with the 7132 “ MASTER ” Dual-Port... | |
| The 71421 is a high-speed 2K x 8 Dual-Port Static RAM with internal interrupt logic for interprocessor communications. It is designed to be used as a “ SLAVE ” Dual-Port... | |
| The 7143 is a high-speed 2K x 16 Dual-Port Static RAMs. Using the IDT MASTER / SLAVE Dual-Port RAM approach in 32-bit-or-wider memory system applications results in full-speed, error-free operation... | |
| The 7164 5V CMOS SRAM is organized as 8K x 8. The 7164 offers a reduced power standby mode. The low-power (L) version also offers a battery backup data retention... | |
| The 71T75602 2.5V CMOS Synchronous SRAM organized as 512K x 36 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes,... | |
| The 71T75802 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes,... | |
| The 71T75902 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes,... | |
| The 71V016 3.3V CMOS SRAM is organized as 64K x 16. All bidirectional inputs and outputs of the 71V016 are LVTTL -compatible and operation is from a single 3.3V supply. | |
| The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/ GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of... | |
| The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or... | |
| The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or... | |
| The 71V256SA 3.3V CMOS Asynchronous SRAM is organized as 32K x 8. When in standby mode, its very low power characteristics contribute to extended battery life. Under full standby mode... | |
| The 71V25761 3.3V CMOS Synchronous SRAM is organized as 128K x 36 and contains write, data, address and control registers. The burst mode feature offers the highest level of performance... | |
| The 71V30 high-speed 1K x 8 Dual-Port Static RAM is designed to be used as a stand-alone 8-bit Dual-Port SRAM . It has two independent ports with separate control, address,... | |
| The 71V321 is a high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communications. The device provides two independent ports with separate control, address, and I/O... | |
| The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or... | |
| The 71V3557 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or... | |
| The 71V3558 3.3V CMOS Synchronous SRAM is organized as 256K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or... | |
| The 71V3559 3.3V CMOS Synchronous SRAM is organized as 256K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or... | |
| The 71V3576 3.3V CMOS SRAM is organized as 128K x 36. The 71V3576 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of... | |
| The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to... | |
| The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of... |
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