Integrated Device Technology 3.3V 512K x 8 Asynchronous Static RAM Center Pwr & Gnd Pinout 71V424S12PHGI8

Description
The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL -compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.
Datasheet
Description
The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL -compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.
Datasheet

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3.3V 512K x 8 Asynchronous Static RAM Center Pwr & Gnd Pinout - 71V424S12PHGI8 - Integrated Device Technology
San Jose, CA, USA
3.3V 512K x 8 Asynchronous Static RAM Center Pwr & Gnd Pinout
71V424S12PHGI8
3.3V 512K x 8 Asynchronous Static RAM Center Pwr & Gnd Pinout 71V424S12PHGI8
The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL -compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.

The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL -compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 71V424S12PHGI8
Product Name 3.3V 512K x 8 Asynchronous Static RAM Center Pwr & Gnd Pinout
Memory Category SRAM Chip
Access Time 12 ns
Operating Temperature -40 to 85 C (-40 to 185 F)
Density 4096 kbits
Number of Words 512 k
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