The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM , or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM .
256K X 36 3.3V Synchronous ZBT SRAM 2.5V I/O, Burst Counter Pipelined Output
| Integrated Device Technology | Rochester Electronics | |
|---|---|---|
| Product Category | Memory Chips | Memory Chips |
| Product Number | 71V65603S100BQG | 71V65603S100BQG |
| Product Name | 3.3V 256K X 36 ZBT Synchronous 3.3V I/O PipeLined SRAM | |
| Memory Category | SRAM Chip | SRAM Chip |
| Data Rate | 100 MHz | |
| Operating Temperature | 0 to 70 C (32 to 158 F) | |
| Density | 256 kbits | |
| Number of Words | 256 k |
