The 71V546 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM , or Zero Bus Turn-around. The 71V546 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM .
| Integrated Device Technology | |
|---|---|
| Product Category | Memory Chips |
| Product Number | 71V546S100PFGI8 |
| Product Name | 3.3V 128K x 36 ZBT Synchronous PipeLined SRAM |
| Memory Category | SRAM Chip |
| Data Rate | 100 MHz |
| Operating Temperature | -40 to 85 C (-40 to 185 F) |
| Density | 128 kbits |
| Number of Words | 128 k |
