Integrated Device Technology 3.3V 128K x 36 ZBT Synchronous Flow-Through SRAM 71V547S100PFGI

Description
The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM , or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM .
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Description
The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM , or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM .
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Suppliers

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Product
Description
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3.3V 128K x 36 ZBT Synchronous Flow-Through SRAM - 71V547S100PFGI - Integrated Device Technology
San Jose, CA, USA
3.3V 128K x 36 ZBT Synchronous Flow-Through SRAM
71V547S100PFGI
3.3V 128K x 36 ZBT Synchronous Flow-Through SRAM 71V547S100PFGI
The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM , or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM .

The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM , or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM .

Supplier's Site Datasheet
 - 71V547S100PFGI - Rochester Electronics
Newburyport, MA, United States
128K X 36, 3.3V Synchronous SRAM With ZBT Feature, Burst Counter And Flow-Through Output

128K X 36, 3.3V Synchronous SRAM With ZBT Feature, Burst Counter And Flow-Through Output

Supplier's Site Datasheet
Integrated Circuits (ICs) - Memory - Memory - 71V547S100PFGI - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Memory - Memory
71V547S100PFGI
Integrated Circuits (ICs) - Memory - Memory 71V547S100PFGI
IC SRAM 4.5MBIT PARALLEL 100TQFP

IC SRAM 4.5MBIT PARALLEL 100TQFP

Supplier's Site
Memory - 71V547S100PFGI - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
SRAM - Synchronous, SDR (ZBT) Memory IC 4.5Mbit Parallel 10 ns 100-TQFP (14x14)

SRAM - Synchronous, SDR (ZBT) Memory IC 4.5Mbit Parallel 10 ns 100-TQFP (14x14)

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Technical Specifications

  Integrated Device Technology Rochester Electronics Shenzhen Shengyu Electronics Technology Limited Quarktwin Technology Ltd.
Product Category Memory Chips Memory Chips Memory Chips Memory Chips
Product Number 71V547S100PFGI 71V547S100PFGI 71V547S100PFGI 71V547S100PFGI
Product Name 3.3V 128K x 36 ZBT Synchronous Flow-Through SRAM Integrated Circuits (ICs) - Memory - Memory Memory
Memory Category SRAM Chip SRAM Chip Volatile; SRAM Chip SRAM; SRAM Chip
Data Rate 100 MHz
Operating Temperature -40 to 85 C (-40 to 185 F) -40 to 85 C (-40 to 185 F)
Density 128 kbits 4500 kbits 4500 kbits
Number of Words 128 k
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