The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/ GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL -compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.
Standard SRAM, 128KX8, 15ns, CMOS, PDSO32
IC SRAM 1MBIT PARALLEL 32SOJ
SRAM - Asynchronous Memory IC 1Mbit Parallel 15 ns 32-SOJ
| Integrated Device Technology | Rochester Electronics | Shenzhen Shengyu Electronics Technology Limited | Quarktwin Technology Ltd. | |
|---|---|---|---|---|
| Product Category | Memory Chips | Memory Chips | Memory Chips | Memory Chips |
| Product Number | 71V124SA15YG | 71V124SA15YG | 71V124SA15YG | 71V124SA15YG |
| Product Name | 3.3V 128K x 8 Asynchronous Static RAM Center Power & Ground Pinout | Integrated Circuits (ICs) - Memory - Memory | Memory | |
| Memory Category | SRAM Chip | SRAM Chip | Volatile; SRAM Chip | SRAM; SRAM Chip |
| Access Time | 15 ns | 15 ns | ||
| Operating Temperature | 0 to 70 C (32 to 158 F) | 0 to 70 C (32 to 158 F) | ||
| Density | 1024 kbits | 1000 kbits | 1000 kbits | |
| Number of Words | 128 k |
