Integrated Device Technology 3.3V 128K x 36 Synchronous PipeLined Burst SRAM w/3.3V I/O 71V35761S200PFG

Description
The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM .
Datasheet
Description
The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM .
Datasheet

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3.3V 128K x 36 Synchronous PipeLined Burst SRAM w/3.3V I/O - 71V35761S200PFG - Integrated Device Technology
San Jose, CA, USA
3.3V 128K x 36 Synchronous PipeLined Burst SRAM w/3.3V I/O
71V35761S200PFG
3.3V 128K x 36 Synchronous PipeLined Burst SRAM w/3.3V I/O 71V35761S200PFG
The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM .

The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM .

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Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 71V35761S200PFG
Product Name 3.3V 128K x 36 Synchronous PipeLined Burst SRAM w/3.3V I/O
Memory Category SRAM Chip
Data Rate 200 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 4608 kbits
Number of Words 128 k
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