The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM , or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.
| Integrated Device Technology | |
|---|---|
| Product Category | Memory Chips |
| Product Number | 71V3556SA100BQGI8 |
| Product Name | 3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 3.3V I/O |
| Memory Category | SRAM Chip |
| Data Rate | 100 MHz |
| Operating Temperature | -40 to 85 C (-40 to 185 F) |
| Density | 4608 kbits |
| Number of Words | 128 k |
