The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM , or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM .
SRAM - Synchronous, SDR (ZBT) Memory IC 4.5Mbit Parallel 133 MHz 4.2 ns 100-TQFP (14x14)
IC SRAM 4.5MBIT PARALLEL 100TQFP
| Integrated Device Technology | Quarktwin Technology Ltd. | Shenzhen Shengyu Electronics Technology Limited | |
|---|---|---|---|
| Product Category | Memory Chips | Memory Chips | Memory Chips |
| Product Number | 71V2556S133PFGI | 71V2556S133PFGI | 71V2556S133PFGI |
| Product Name | 3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 2.5V I/O | Memory | Integrated Circuits (ICs) - Memory |
| Memory Category | SRAM Chip | SRAM; SRAM Chip | Volatile; SRAM Chip |
| Data Rate | 133 MHz | 133 MHz | |
| Operating Temperature | -40 to 85 C (-40 to 185 F) | -40 to 85 C (-40 to 185 F) | -40 to 85 C (-40 to 185 F) |
| Density | 4608 kbits | 4500 kbits | 4500 kbits |
| Number of Words | 128 k |
