The 71V3557 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM , or Zero Bus Turnaround. The 71V3557 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).
SRAM - Synchronous, SDR (ZBT) Memory IC 4.5Mbit Parallel 8.5 ns 119-PBGA (14x22)
IC SRAM 4.5MBIT PARALLEL 119PBGA
| Integrated Device Technology | Quarktwin Technology Ltd. | Shenzhen Shengyu Electronics Technology Limited | |
|---|---|---|---|
| Product Category | Memory Chips | Memory Chips | Memory Chips |
| Product Number | 71V3557S85BG | 71V3557S85BG | 71V3557S85BG |
| Product Name | 3.3V 128Kx36 ZBT Synchronous Flow-Through SRAM with 3.3V I/O | Memory | Integrated Circuits (ICs) - Memory - Memory |
| Memory Category | SRAM Chip | SRAM; SRAM Chip | Volatile; SRAM Chip |
| Cycle Time | 85 ns | 8.5 ns | |
| Operating Temperature | 0 to 70 C (32 to 158 F) | 0 to 70 C (32 to 158 F) | |
| Density | 128 kbits | 4500 kbits | 4500 kbits |
| Number of Words | 128 k |
