The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM , or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM .
| Integrated Device Technology | |
|---|---|
| Product Category | Memory Chips |
| Product Number | 71V2556SA100BG8 |
| Product Name | 3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 2.5V I/O |
| Memory Category | SRAM Chip |
| Data Rate | 100 MHz |
| Operating Temperature | 0 to 70 C (32 to 158 F) |
| Density | 4608 kbits |
| Number of Words | 128 k |
