The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/ GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL -compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.
| Integrated Device Technology | |
|---|---|
| Product Category | Memory Chips |
| Product Number | 71V124SA12PHG8 |
| Product Name | 3.3V 128K x 8 Asynchronous Static RAM Center Power & Ground Pinout |
| Memory Category | SRAM Chip |
| Access Time | 12 ns |
| Operating Temperature | 0 to 70 C (32 to 158 F) |
| Density | 1024 kbits |
| Number of Words | 128 k |
