The 71V3557 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM , or Zero Bus Turnaround. The 71V3557 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).
| Integrated Device Technology | |
|---|---|
| Product Category | Memory Chips |
| Product Number | 71V3557S75BG8 |
| Product Name | 3.3V 128Kx36 ZBT Synchronous Flow-Through SRAM with 3.3V I/O |
| Memory Category | SRAM Chip |
| Cycle Time | 75 ns |
| Operating Temperature | 0 to 70 C (32 to 158 F) |
| Density | 128 kbits |
| Number of Words | 128 k |
