Microchip Technology, Inc. Datasheets for Logic Dividers
Logic dividers are integrated circuits that divide the frequency of an input signal by a divisor value.
Logic Dividers: Learn more
| Product Name | Notes |
|---|---|
| The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common... | |
| The SY100EL32V is an integrated divide by 2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB... | |
| The SY100EL33L are integrated ÷4 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be... | |
| The SY100EP32V is an integrated ÷2 divider with differential clock inputs. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the... | |
| The SY100EP33V is an integrated ÷4 divider. The VBB pin, an internally-generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected... | |
| The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each... | |
| The SY100S839V is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common... | |
| The SY89200U is a 2.5V precision, high-speed, integrated clock divider and LVDS fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the three independently controlled output... | |
| The SY89202U is a precision, high-speed, integrated clock divider LVPECL fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the three independently controlled output banks are... | |
| The SY89218U is a 2.5V precision, high-speed, integrated clock divider and LVDS fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the four independently controlled output... | |
| The SY89221U is a 2.5/3.3V precision, high-speed, integrated clock divider and LVPECL fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the four independently controlled output... | |
| The SY89228U is a precision, low jitter 1GHz ÷3, ÷5 clock divider with an LVPECL output. A unique Fail-Safe Input (FSI) protection prevents metastable output conditions when the input clock... | |
| The SY89230U is a precision, low jitter 3.2GHz ÷3, ÷5 clock divider with a LVPECL output. The differential input includes Micrel's unique, 3-pin internal termination architecture that allows the input... | |
| The SY89231U is a precision, low jitter 3.2GHz ÷3, ÷5 clock divider with a LVDS output. The differential input includes Micrel's unique, 3-pin internal termination architecture that allows the input... | |
| The SY89312V is an integrated ÷2 divider with differential clock inputs. It is functionally equivalent to the SY100EP32V but in an ultra-small 8-lead MLF® package that features a 70% smaller... | |
| The SY89313V is a differential ECL/PECL integrated ÷4 divider clock generator. It is functionally equivalent to the SY100EP33V but in an ultra-small 8-lead MLF® package that features a 70% smaller... | |
| The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and... | |
| This 2.5V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a... | |
| This 3.3V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC- or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a... | |
| This low-skew, low-jitter device can accept a high-speed (622MHz or higher) LVTTL, LVCMOS, CML, LVPECL, LVDS or HSTL clock input signal and divide down the frequency using a programmable divider... | |
| This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable... |