Microchip Technology, Inc. SY100EL32V

Description
The SY100EL32V is an integrated divide by 2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only; the VBB output has limited current sink and source capability. The Reset pin is asynchronous and is asserted on the rising edge. Upon power-on, the internal flip-flop will attain a random state. The Reset allows for the synchronization of multiple EL32Vs in a system.
Datasheet
Description
The SY100EL32V is an integrated divide by 2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only; the VBB output has limited current sink and source capability. The Reset pin is asynchronous and is asserted on the rising edge. Upon power-on, the internal flip-flop will attain a random state. The Reset allows for the synchronization of multiple EL32Vs in a system.
Datasheet

Suppliers

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Description
Supplier Links
 - SY100EL32V - Microchip Technology, Inc.
Chandler, AZ, United States
The SY100EL32V is an integrated divide by 2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only; the VBB output has limited current sink and source capability. The Reset pin is asynchronous and is asserted on the rising edge. Upon power-on, the internal flip-flop will attain a random state. The Reset allows for the synchronization of multiple EL32Vs in a system.

The SY100EL32V is an integrated divide by 2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only; the VBB output has limited current sink and source capability. The Reset pin is asynchronous and is asserted on the rising edge. Upon power-on, the internal flip-flop will attain a random state. The Reset allows for the synchronization of multiple EL32Vs in a system.

Supplier's Site Datasheet

Technical Specifications

  Microchip Technology, Inc.
Product Category Logic Dividers
Product Number SY100EL32V
Package Type SOIC; ['SOIC']
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