This 3.3V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC- or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89873L includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to all AC- or DC-coupled differential logic standards. A VREF-AC reference is included for AC-coupled applications.The SY89873L is part of Micrel's high-speed Precision Edge® timing and distribution family. For 2.5V applications, consider the SY89872U. For applications that require an LVPECL output, consider the SY89871U.The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N). Refer to the Timing Diagram.
Additional Features
Guaranteed AC performance
>2.0GHz fMAX output toggle
>3.0GHz fMAX input
<800ps tPD (matched-delay between banks)
<15ps within-device skew
<190ps rise/fall time
Low jitter design
<1psRMS cycle-to-cycle jitter
Unique input termination and VTpin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
Precision differential LVDS outputs
Matched delay: all outputs have matched delay, independent of divider setting
TTL/CMOS inputs for select and reset/disable
Two LVDS output banks (matched delay)
Bank A: Buffered copy of input clock (undivided)
Bank B: Divided output (÷2, ÷4, ÷8, ÷16), two copies
3.3V power supply
Wide operating temperature range: -40°C to +85°C
Available in 16-pin (3mm x 3mm) QFN package
This 3.3V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC- or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89873L includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components.
The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to all AC- or DC-coupled differential logic standards. A VREF-AC reference is included for AC-coupled applications.The SY89873L is part of Micrel's high-speed Precision Edge® timing and distribution family. For 2.5V applications, consider the SY89872U. For applications that require an LVPECL output, consider the SY89871U.The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N). Refer to the Timing Diagram.
Additional Features
- Guaranteed AC performance
- >2.0GHz fMAX output toggle
- >3.0GHz fMAX input
- <800ps tPD (matched-delay between banks)
- <15ps within-device skew
- <190ps rise/fall time
- Low jitter design
- <1psRMS cycle-to-cycle jitter
- Unique input termination and VTpin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
- Precision differential LVDS outputs
- Matched delay: all outputs have matched delay, independent of divider setting
- TTL/CMOS inputs for select and reset/disable
- Two LVDS output banks (matched delay)
- Bank A: Buffered copy of input clock (undivided)
- Bank B: Divided output (÷2, ÷4, ÷8, ÷16), two copies
- 3.3V power supply
- Wide operating temperature range: -40°C to +85°C
- Available in 16-pin (3mm x 3mm) QFN package
