Integrated Device Technology Datasheets for SRAM Memory Chips
Static random access memory (SRAM) chips do not need to be refreshed like DRAM chips. This makes SRAM chips faster and more reliable.
SRAM Memory Chips: Learn more
| Product Name | Notes |
|---|---|
| The 71V3559 3.3V CMOS Synchronous SRAM is organized as 256K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or... | |
| The 71V3576 3.3V CMOS SRAM is organized as 128K x 36. The 71V3576 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of... | |
| The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to... | |
| The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of... | |
| The 71V3578 3.3V CMOS SRAM is organized as 256K x 18. The 71V3578 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of... | |
| The 71V3579 3.3V CMOS SRAM is organized as 256K x 18. The 71V3579 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of... | |
| The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL -compatible and operation is from a single 3.3V supply. | |
| The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL -compatible and operation is from a single 3.3V supply. | |
| The 71V546 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or... | |
| The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or... | |
| The 71V632 3.3V CMOS SRAM is organized as 64K x 32. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz. The 71V632 SRAM contains... | |
| The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes... | |
| The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes... |
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