Integrated Device Technology Datasheets for IC Interfaces
IC interfaces are semiconductor chips that are used to control and manage the sharing of information between devices.
IC Interfaces: Learn more
| Product Name | Notes |
|---|---|
| Alternative Products NOTICE - The following device(s) are recommended alternatives: 74FCT38074S - Low Skew 1 to 4 Clock Buffer Improved jitter performance, smaller package The FCT38074 is a 3.3V clock... | |
| Alternative Products NOTICE - The following device(s) are recommended alternatives: 74FCT38075S - Low Skew 1 to 5 Clock Buffer Improved jitter performance, smaller package The FCT38075 is a 3.3V clock... | |
| Alternative Products NOTICE - The following device(s) are recommended alternatives: 74FCT3807S - Low Skew 1 to 10 Clock Buffer Improved jitter performance, smaller package The FCT3807 /A 3.3V clock driver... | |
| Alternative Products NOTICE - The following device(s) are recommended alternatives: 74FCT3807S - Low Skew 1 to 10 Clock Buffer Improved jitter performance, smaller package The FCT3807 is a 3.3V clock... | |
| The 621 is a low skew, single input to four output, clock buffer. The device operates from a single 1.2 to 1.8 volt supply and has a 3.3 volt tolerant... | |
| The 621S is a low cost, high-speed single input to four output LVCMOS clock buffer. The 621S has best in class Additive Phase Jitter of sub 50 fsec. | |
| The 651 is a low skew, single input to four output, clock buffer. Part of IDT ’s ClockBlocksTM family, this is a low skew, small clock buffer. IDT makes many... | |
| The 651S is a low cost, high-speed single input to four output LVCMOS clock buffer. The 651S has best in class Additive Phase Jitter of sub 50 fsec. | |
| The 670-01 is a high speed, low phase noise, Zero Delay Buffer ( ZDB ) which integrates IDT 's proprietary analog/digital Phase Locked Loop ( PLL ) techniques. Part of... | |
| The 672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on IDT 's proprietary low jitter Phase-Locked Loop ( PLL )... | |
| The 674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider... | |
| The 6P30006A is a low-power, eight output clock distribution circuit. The device takes a TCXO or LVCMOS input and generates eight high-quality outputs. It includes a redundant input with automatic... | |
| The 74ALVC162244 16-bit buffer/driver is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used... | |
| The 74ALVC162245 16-bit bus transceiver is designed for asynchronous communication between data buses and can be used as two 8-bit transceivers or one 16-bit transceiver. The output-enable ( OE )... | |
| The 74ALVC162334 is a 16-bit universal bus driver that has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver... | |
| The 74ALVC16244 16-bit buffer/driver is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used... | |
| The 74ALVC16245 16-bit bus transceiver is designed for asynchronous communication between data buses and can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission between... | |
| The 74ALVC164245 16-bit 3.3V to 5V level shifting transceiver contains two separate supply rails; B port has VCCB , which is set at 5V, and A port has VCCA ,... | |
| The 74ALVCH162244 16-bit buffer/driver is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used... | |
| The 74ALVCH162245 16-bit bus transceiver is designed for asynchronous communication between data buses and can be used as two 8-bit transceivers or one 16-bit transceiver. The 74ALVCH162245 has series resistors... | |
| The 74ALVCH16244 16-bit buffer/driver is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used... | |
| The 74ALVCH16245 16-bit bus transceiver is designed for asynchronous communication between data buses and can be used as two 8-bit transceivers or one 16-bit transceiver. The 74ALVCH16245 has “bus-hold” which... | |
| The 74ALVCH32244 high-speed, low power 32-bit buffer/driver offers bus/backplane interface capability with improved packing density. The three-state controls operate this device in a Quad-Nibble, Dual-Byte or single 16-bit word mode. | |
| The 74ALVCH32245 high-speed, low power 32-bit bus transceiver is ideal for asynchronous communication between two busses. The Direction and Output Enable controls are designed to operate the device as either... | |
| The 74ALVCHR162245 16-bit bus transceiver is designed for asynchronous communication between data buses. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission... | |
| The 74FC244T octal buffer/line driver is designed to be employed as a memory and address driver, clock driver, and bus-oriented transmitter/ receiver which provides improved board density. The 74FCT244T operates... | |
| The 74FCT162244T 16-Bit high speed, low power Buffer/Line Driver can operate as independent 4-bit, 8-bit or combined 16-bit operation. The 74FCT162244T reduces the need for external series terminating resistors while... | |
| The 74FCT162245T 16-bit high-speed, low-power transceiver is ideal for synchronous communication between two buses and can operate as either two independent 8-bit transceivers or one 16-bit transceiver. The 74FCT162245T offers... | |
| The 74FCT16244T 16-Bit Buffer/Line Driver is for bus interface or signal buffering applications and can operate as independent 4-bit, 8-bit or combined 16-bit operation. The 74FCT16244T is ideally suited for... | |
| The 74FCT16245T 16-bit high-speed, low-power transceiver is ideal for synchronous communication between two busses. It can operate as either two independent 8-bit transceivers or one 16-bit transceiver. The 74FCT16245T is... | |
| The 74FCT162827T 20-bit buffers provide high-performance bus interface buffering for wide data/address paths or buses carrying parity. The device can operate as two 10-bit buffers or one 20-bit buffer. The... | |
| The 74FCT163244 16-bit high-speed, low-power buffer/line drivers offer bus/ backplane interface capability with improved packing density. The three-state controls operate these devices in a Quad-Nibble, Dual-Byte or single 16-bit word... | |
| The 74FCT163245 16-bit high-speed, low-power transceivers are ideal for asynchronous communication between two buses. The Direction and Output Enable controls are designed to operate these devices as either two independent... | |
| The 74FCT163827 20-bit buffer provide high-performance bus interface buffering for wide data/address paths or busses carrying parity. The 74FCT163827 has series current limiting resistors reducing the need for external series... | |
| The 74FCT164245T 16-bit high-speed, low-power 3.3V-to-5V translator is designed to interface between a 3.3V bus and a 5V bus in a mixed 3.3V/ 5V supply environment. This enables system designers... | |
| The 74FCT16543T 16-bit high-speed, low-power latched transceiver is organized as two independent 8-bit D-type latched transceivers with separate input and output control to permit independent control of data flow in... | |
| The 74FCT16952T 16-bit high-speed, low-power registered transceiver is organized as two independent 8-bit D-type registered transceivers with separate input and output control for independent control of data flow in either... | |
| The 74FCT2244T Octal Buffer/Line Driver is designed to be employed as a memory and address driver, clock driver, and bus-oriented transmitter/receiver which provides improved board density. The octal buffer has... | |
| The 74FCT2245T octal bidirectional transceiver is designed for asynchronous two-way communication between data buses. The transmit/receive (T/R) input determines the direction of data flow through the bidirectional transceiver. The 74FCT2245T... | |
| The 74FCT240T octal buffer/line driver is designed to be employed as a memory and address driver, clock driver, and bus-oriented transmitter/ receiver which provides improved board density. The 74FCT240T operates... | |
| The 74FCT245T octal bidirectional transceiver is designed for asynchronous two way communication between data buses. The transmit/receive (T/R) input determines the direction of data flow through the bidirectional transceiver. The... | |
| The 74FCT3244 octal high-speed, low-power buffer/line driver is designed to be used as memory data and address drivers, clock drivers, and bus-oriented transmitter/receiver s. The three-state controls are designed to... | |
| The 74FCT3245 octal high-speed, low-power transceiver is ideal for asynchronous communication between two buses. The direction control pin ( DIR ) controls the direction of data flow. The output enable... | |
| The 74FCT38072S is a low skew, single input to two output, LVCMOS clock buffer. The 74FCT38072S has best in class additive phase Jitter of sub 50 fsec. | |
| The 74FCT38074S is a low skew, single input to four output, LVCMOS clock buffer. The 74FCT38074S has best in class additive phase Jitter of sub 50 fsec. | |
| The 74FCT38075S is a low skew, single input to five output, LVCMOS clock buffer. The 74FCT38075S has best in class additive phase Jitter of sub 50 fsec. | |
| The 74FCT3807S is a low skew, single input to ten output, LVCMOS clock buffer. The 74FCT3807S has best in class additive phase Jitter of sub 50 fsec. | |
| The 74FCT540T octal buffer/line driver is similar in function to the FCT240T , except that the inputs and outputs are on opposite sides of the package. This pinout arrangement makes... | |
| The 74FCT621T is an octal transceiver with non-inverting Open- Drain bus compatible outputs in both send and receive directions. The B bus outputs are capable of sinking 64mA providing very... | |
| The 74LVC162244A 16-bit buffer/driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters and can be used... | |
| The 74LVC16244A 16-bit buffer/driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters and can be used... | |
| The FCT807T clock driver is built using advanced dual metal CMOS technology. This low skew clock driver features 1:10 fanout, providing minimal loading on the preceding drivers. The FCT807T offers... | |
| The ICS670 -02 is a high speed, low phase noise, Zero Delay Buffer ( ZDB ) which integrates IDT ’s proprietary analog/digital Phase Locked Loop ( PLL ) techniques. Part... | |
| The ICS670 -03 is a high speed, low phase noise, Zero Delay Buffer ( ZDB ) which integrates IDT ’s proprietary analog/digital Phase Locked Loop ( PLL ) techniques. It... | |
| The ICS670 -04 is a high speed, low phase noise, Zero Delay Buffer ( ZDB ) which integrates IDT ’s proprietary analog/digital Phase Locked Loop ( PLL ) techniques. It... | |
| The IDT6P61043 is a 4-output very low power buffer for 100MHz PCIe Gen1, Gen2 and Gen3 applications with integrated output terminations providing Zo=100Ω for Freescale Systems. The device has 4... | |
| The IDT6T39007A is a low-power, four output clock distribution circuit. The device takes a TCXO or 1.8 V to 2.5 V LVCMOS input and generates four high-quality LVDS outputs, and... | |
| The IDT6V31021 is a 4-output low- power differential buffer. Each output has its own OE # pin. It has a maximum operating frequency of 167 MHz and supports all SERDES... | |
| The LVC162245A is designed for asynchronous communication between data buses and can be used as two 8-bit transceivers or one 16-bit transceiver. The output-enable ( OE ) input can be... |
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