Integrated Device Technology 3.3V Zero Delay Clock Buffer, Spread Spectrum Compatible 23S09-1DCG

The IDT23S09 is a high-speed phase-lock loop ( PLL ) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT23S09 is a 16-pin version of the IDT23S05 . The IDT23S09accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT23S09 enters power down. In this mode, the device will draw less than 12μA for Commercial Temperature range and less than 25μA for Industrialtemperatur e range, and the outputs are tri-stated. The IDT23S09 is characterized for both Industrial and Commercial operation.