Integrated Device Technology Datasheets for FIFO Memory
First-in, first-out (FIFO) memory chips are used in buffering applications between devices that operate at different speeds or in applications where data must be stored temporarily for further processing.
FIFO Memory: Learn more
| Product Name | Notes |
|---|---|
| The 72V263 16K x 9/8K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the... | |
| The 72V265 is an 16K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72265 designed to run off a 3.3V... | |
| The 72V271 is a 32K x 9 SuperSync FIFO memory with clocked read and write controls. It’s a functionally compatible version of the 72271 designed to run off a 3.3V... | |
| The 72V273 32K x 9/16K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the... | |
| The 72V275 is a 32K x 18 SuperSync FIFO memory with clocked read and write controls. It’s a functionally compatible version of the 72275 designed to run off a 3.3V... | |
| The 72V281 is a 64K x 9 SuperSync FIFO memory with clocked read and write controls. It’s a functionally compatible version of the 72281 designed to run off a 3.3V... | |
| The 72V283 64K x 9/32K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the... | |
| The 72V285 is an 64K x 18 SuperSync FIFO memory with clocked read and write controls. It’s a functionally compatible version of the 72285 designed to run off a 3.3V... | |
| The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It’s a functionally compatible version of the 72291 designed to run off a 3.3V... | |
| The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the... | |
| The 72V295 is an 128K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin ( FS ) has been removed, thus it is no... | |
| The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchro nous translation on the read or write... | |
| The 72V3611 is a 64 x 36 3.3V Sync FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. Communication between each... | |
| The 72V36110 128K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchro nous translation on the read or write... | |
| The 72V3612 is a 3.3V version of the 723612. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Communication between each port... | |
| The 72V3622 is a 3.3V version of the 723622. Two independent 256 x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may... | |
| The 72V3623 is a 256 x 36 Sync FIFO that is a 3.3V version of the 723623. The clocks for each port are independent of one another and can be... | |
| The 72V3624 is a 3.3V version of the IDT723624 . Two independent 256 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. | |
| The 72V3631is a 512 x 36 Sync FIFO memory that is a 3.3V version of the 723631. It supports clock frequencies up to 67 MHz and has read access times... | |
| The 72V3632 is a 3.3V version of the 723632. Two independent 512 x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may... | |
| The 72V3640 1K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchro nous translation on the read or write... | |
| The 72V3641is a 1K x 36 Sync FIFO memory that is a 3.3V version of the 723641. It supports clock frequencies up to 67 MHz and has read access times... | |
| The 72V3642 is a 3.3V version of the 723642. Two independent 1K x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may... | |
| The 72V3643 is a 1K x 36 Sync FIFO that is a 3.3V version of the 723643. The clocks for each port are independent of one another and can be... | |
| The 72V3644 is a 3.3V version of the IDT723644 . Two independent 1,024 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. | |
| The 72V3650 2K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchro nous translation on the read or write... | |
| The 72V3653 is a 2K x 36 Sync FIFO memory. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each... | |
| The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to... | |
| The 72V3660 4K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchro nous translation on the read or write... | |
| The 72V3663 is a 4K x 36 Sync FIFO that is a 3.3V version of the 723663. The clocks for each port are independent of one another and can be... | |
| The 72V3664 is a 3.3V bidirectional synchronous (clocked) FIFO . Two independent 4K x 36 dualport SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for... | |
| The 72V3670 8K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchro nous translation on the read or write... | |
| The 72V3672 Bidirectional SyncFIFO (clocked) memory is a 3.3V version of the 723672. Two independent 8K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. | |
| The 72V3673 is a 8K x 36 Sync FIFO that is a 3.3V version of the 723673. The clocks for each port are independent of one another and can be... | |
| The 72V3680 16K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchro nous translation on the read or write... | |
| The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchro nous translation on the read or write... | |
| The 72V51253 multi-queue flow-control device is a single chip within which between 1 and 4 discrete FIFO queues can be setup. All queues within the device have common data input... | |
| The 72V51256 multi-queue flow-control device is a single chip within which between 1 and 4 discrete FIFO queues can be setup. All queues within the device have a common data... | |
| The 72V51443 multi-queue flow-control device is a single chip within which between 1 and 16 discrete FIFO queues can be setup. All queues within the device have common data input... | |
| The 72V51446 multi-queue flow-control device is a single chip within which between 1 and 16 discrete FIFO queues can be setup. All queues within the device have common data input... | |
| The 72V51456 multi-queue flow-control device is a single chip within which between 1 and 16 discrete FIFO queues can be setup. All queues within the device have common data input... | |
| The 72V801is a 256 x 9 dual synchronous FIFO that is functionally equivalent to two 72V201 FIFOs in a single package with all associated control, data, and flag lines assigned... | |
| The 72V805 is a 256 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V205 FIFO ’s in a single package with... | |
| The 72V81 is a dual- FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits... | |
| The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned... | |
| The 72V815 is a 512 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V215 FIFO ’s in a single package with... | |
| The 72V82 is a dual- FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits... | |
| The 72V821is a 1K x 9 dual synchronous FIFO that is functionally equivalent to two 72V221 FIFOs in a single package with all associated control, data, and flag lines assigned... | |
| The 72V825 is a 1K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V225 FIFO ’s in a single package with... | |
| The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned... |
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