Integrated Device Technology 8K x 36 SyncFIFO, 3.3V 72V3673L15PF8

Description
The 72V3673 is a 8K x 36 Sync FIFO that is a 3.3V version of the 723673. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. The FIFO has Retransmit capability which resets the read pointer to the first memory location. This device can operate in IDT Standard mode or First Word Fall Through mode.
Datasheet
Description
The 72V3673 is a 8K x 36 Sync FIFO that is a 3.3V version of the 723673. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. The FIFO has Retransmit capability which resets the read pointer to the first memory location. This device can operate in IDT Standard mode or First Word Fall Through mode.
Datasheet

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8K x 36 SyncFIFO, 3.3V - 72V3673L15PF8 - Integrated Device Technology
San Jose, CA, USA
8K x 36 SyncFIFO, 3.3V
72V3673L15PF8
8K x 36 SyncFIFO, 3.3V 72V3673L15PF8
The 72V3673 is a 8K x 36 Sync FIFO that is a 3.3V version of the 723673. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. The FIFO has Retransmit capability which resets the read pointer to the first memory location. This device can operate in IDT Standard mode or First Word Fall Through mode.

The 72V3673 is a 8K x 36 Sync FIFO that is a 3.3V version of the 723673. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. The FIFO has Retransmit capability which resets the read pointer to the first memory location. This device can operate in IDT Standard mode or First Word Fall Through mode.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72V3673L15PF8
Product Name 8K x 36 SyncFIFO, 3.3V
Memory Category FIFO
Logic Family TTL
Data Rate 66 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 288 kbits
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