Integrated Device Technology 64 x 36 SyncFIFO, 3.3V 72V3611L15PFG8

Description
The 72V3611 is a 64 x 36 3.3V Sync FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. Communication between each port can take place through two 36-bit mailbox registers. Two or more devices may be used in parallel to create wider data paths. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
Datasheet
Description
The 72V3611 is a 64 x 36 3.3V Sync FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. Communication between each port can take place through two 36-bit mailbox registers. Two or more devices may be used in parallel to create wider data paths. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
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64 x 36 SyncFIFO, 3.3V - 72V3611L15PFG8 - Integrated Device Technology
San Jose, CA, USA
64 x 36 SyncFIFO, 3.3V
72V3611L15PFG8
64 x 36 SyncFIFO, 3.3V 72V3611L15PFG8
The 72V3611 is a 64 x 36 3.3V Sync FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. Communication between each port can take place through two 36-bit mailbox registers. Two or more devices may be used in parallel to create wider data paths. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The 72V3611 is a 64 x 36 3.3V Sync FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. Communication between each port can take place through two 36-bit mailbox registers. Two or more devices may be used in parallel to create wider data paths. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72V3611L15PFG8
Product Name 64 x 36 SyncFIFO, 3.3V
Memory Category FIFO
Logic Family TTL
Data Rate 66 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 2 kbits
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