Integrated Device Technology 1K x 36 x 2 SyncBiFIFO, 3.3V 72V3642L10PFG

Description
The 72V3642 is a 3.3V version of the 723642. Two independent 1K x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
Datasheet
Description
The 72V3642 is a 3.3V version of the 723642. Two independent 1K x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
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1K x 36 x 2 SyncBiFIFO, 3.3V - 72V3642L10PFG - Integrated Device Technology
San Jose, CA, USA
1K x 36 x 2 SyncBiFIFO, 3.3V
72V3642L10PFG
1K x 36 x 2 SyncBiFIFO, 3.3V 72V3642L10PFG
The 72V3642 is a 3.3V version of the 723642. Two independent 1K x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The 72V3642 is a 3.3V version of the 723642. Two independent 1K x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

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Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72V3642L10PFG
Product Name 1K x 36 x 2 SyncBiFIFO, 3.3V
Memory Category FIFO
Logic Family TTL
Data Rate 100 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 72 kbits
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