Integrated Device Technology 4Q x18 2M Multi-Queue, 3.3V 72V51253L6BB8

Description
The 72V51253 multi-queue flow-control device is a single chip within which between 1 and 4 discrete FIFO queues can be setup. All queues within the device have common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user.
Datasheet
Description
The 72V51253 multi-queue flow-control device is a single chip within which between 1 and 4 discrete FIFO queues can be setup. All queues within the device have common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user.
Datasheet

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4Q x18 2M Multi-Queue, 3.3V - 72V51253L6BB8 - Integrated Device Technology
San Jose, CA, USA
4Q x18 2M Multi-Queue, 3.3V
72V51253L6BB8
4Q x18 2M Multi-Queue, 3.3V 72V51253L6BB8
The 72V51253 multi-queue flow-control device is a single chip within which between 1 and 4 discrete FIFO queues can be setup. All queues within the device have common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user.

The 72V51253 multi-queue flow-control device is a single chip within which between 1 and 4 discrete FIFO queues can be setup. All queues within the device have common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72V51253L6BB8
Product Name 4Q x18 2M Multi-Queue, 3.3V
Memory Category FIFO
Logic Family TTL
Data Rate 166 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 2048 kbits
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