Integrated Device Technology 2K x 36 x 2 Triple-Bus FIFO, 3.3V 72V3656L10PF

Description
The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO ’s can be combined with unidirectional FIFO ’s capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion.
Datasheet
Description
The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO ’s can be combined with unidirectional FIFO ’s capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion.
Datasheet

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2K x 36 x 2 Triple-Bus FIFO, 3.3V - 72V3656L10PF - Integrated Device Technology
San Jose, CA, USA
2K x 36 x 2 Triple-Bus FIFO, 3.3V
72V3656L10PF
2K x 36 x 2 Triple-Bus FIFO, 3.3V 72V3656L10PF
The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO ’s can be combined with unidirectional FIFO ’s capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion.

The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO ’s can be combined with unidirectional FIFO ’s capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72V3656L10PF
Product Name 2K x 36 x 2 Triple-Bus FIFO, 3.3V
Memory Category FIFO
Logic Family TTL
Data Rate 100 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 144 kbits
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