The 72V51256 multi-queue flow-control device is a single chip within which between 1 and 4 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user.
| Integrated Device Technology | |
|---|---|
| Product Category | Memory Chips |
| Product Number | 72V51256L7-5BB8 |
| Product Name | 4Q x36 2M Multi-Queue, 3.3V |
| Memory Category | FIFO |
| Logic Family | TTL |
| Data Rate | 133 MHz |
| Operating Temperature | 0 to 70 C (32 to 158 F) |
| Density | 2048 kbits |
