Nexperia B.V. Datasheets for Flip-Flops

Flip-flops are digital logic devices that synchronize changes in output state (1 or 0) according to a clocked input.
Flip-Flops: Learn more

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Product Name Notes
74ABT74 - Dual D-type flip-flop -- 74ABT74DB,118
74AUP1G175 - Low-power D-type flip-flop with reset; positive-edge trigger -- 74AUP1G175GF,132
74AUP1G374 - Low-power D-type flip-flop; positive-edge trigger; 3-state -- 74AUP1G374GF,132
74AUP1G74 - Low-power D-type flip-flop with set and reset; positive-edge trigger -- 74AUP1G74GF,115
74AUP1G74 - Low-power D-type flip-flop with set and reset; positive-edge trigger -- 74AUP1G74GM,125
74AUP1G79 - Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G79GF,132
74AUP1G80 - Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G80GF,132
74AUP2G79 - Low-power dual D-type flip-flop; positive-edge trigger -- 74AUP2G79GF,115
74AUP2G80 - Low-power dual D-type flip-flop; positive-edge trigger -- 74AUP2G80GF,115
74AUP2G80 - Low-power dual D-type flip-flop; positive-edge trigger -- 74AUP2G80GM,125
74HC(T)107 - Dual JK flip-flop with reset; negative-edge trigger -- 74HC107DB,112
74HC(T)107 - Dual JK flip-flop with reset; negative-edge trigger -- 74HC107DB,118
74HC(T)109 - Dual JK flip-flop with set and reset; positive-edge trigger -- 74HC109DB,112
74HC(T)109 - Dual JK flip-flop with set and reset; positive-edge trigger -- 74HC109DB,118
74HC(T)109 - Dual JK flip-flop with set and reset; positive-edge trigger -- 74HCT109DB,112
74HC(T)109 - Dual JK flip-flop with set and reset; positive-edge trigger -- 74HCT109DB,118
74HC(T)112 - dual JK flip-flop with set and reset; negative-edge trigger -- 74HC112DB,112
74HC(T)112 - dual JK flip-flop with set and reset; negative-edge trigger -- 74HC112DB,118
74HC(T)112 - dual JK flip-flop with set and reset; negative-edge trigger -- 74HCT112DB,118
74HC(T)173 - Quad D-type flip-flop; positive-edge trigger; 3-state -- 74HC173DB,112
74HC(T)173 - Quad D-type flip-flop; positive-edge trigger; 3-state -- 74HC173DB,118
74HC(T)173 - Quad D-type flip-flop; positive-edge trigger; 3-state -- 74HCT173DB,118
74HC(T)174 - Hex D-type flip-flop with reset; positive-edge trigger -- 74HC174DB,112
74HC(T)174 - Hex D-type flip-flop with reset; positive-edge trigger -- 74HC174DB,118
74HC(T)174 - Hex D-type flip-flop with reset; positive-edge trigger -- 74HCT174DB,118
74HC(T)175 - Quad D-type flip-flop with reset; positive-edge trigger -- 74HC175DB,118
74HC(T)175 - Quad D-type flip-flop with reset; positive-edge trigger -- 74HCT175DB,118
74HC(T)273 - Octal D-type flip-flop with reset; positive-edge trigger -- 74HC273DB,112
74HC(T)273 - Octal D-type flip-flop with reset; positive-edge trigger -- 74HC273DB,118
74HC(T)273 - Octal D-type flip-flop with reset; positive-edge trigger -- 74HCT273DB,118
74HC(T)374 - Octal D-type flip-flop; positive edge-trigger; 3-state -- 74HC374DB,112
74HC(T)374 - Octal D-type flip-flop; positive edge-trigger; 3-state -- 74HC374DB,118
74HC(T)374 - Octal D-type flip-flop; positive edge-trigger; 3-state -- 74HCT374DB,112
74HC(T)374 - Octal D-type flip-flop; positive edge-trigger; 3-state -- 74HCT374DB,118
74HC(T)377 - Octal D-type flip-flop with data enable; positive-edge trigger -- 74HC377DB,118
74HC(T)377 - Octal D-type flip-flop with data enable; positive-edge trigger -- 74HCT377DB,118
74HC(T)377-Q100 - Octal D-type flip-flop with data enable; positive-edge trigger -- 74HC377DB-Q100J
74HC(T)377-Q100 - Octal D-type flip-flop with data enable; positive-edge trigger -- 74HCT377DB-Q100J
74HC(T)574 - Octal D-type flip-flop; positive edge-trigger; 3-state -- 74HC574DB,112
74HC(T)574 - Octal D-type flip-flop; positive edge-trigger; 3-state -- 74HC574DB,118
74HC(T)574 - Octal D-type flip-flop; positive edge-trigger; 3-state -- 74HCT574DB,112
74HC(T)574 - Octal D-type flip-flop; positive edge-trigger; 3-state -- 74HCT574DB,118
74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HC74DB,112
74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HC74DB,118
74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HCT74DB,112
74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HCT74DB,118
74HC73 - Dual JK flip-flop with reset; negative-edge trigger -- 74HC73DB,118
74LV74 - Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LV74DB,118
74LVC(H)16374A - 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state -- 74LVC16374ADL,112
74LVC(H)16374A - 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state -- 74LVC16374ADL,118
74LVC1G175 - Single D-type flip-flop with reset; positive edge trigger -- 74LVC1G175GF,132
74LVC1G74 - Single D-type flip-flop with set and reset; positive edge trigger -- 74LVC1G74GF,115
74LVC1G74 - Single D-type flip-flop with set and reset; positive edge trigger -- 74LVC1G74GM,125
74LVC1G79 - Single D-type flip-flop; positive-edge trigger -- 74LVC1G79GF,132
74LVC1G80 - Single D-type flip-flop; positive-edge trigger -- 74LVC1G80GF,132
74LVC273 - Octal D-type flip-flop with reset; positive-edge trigger -- 74LVC273DB,112
74LVC273 - Octal D-type flip-flop with reset; positive-edge trigger -- 74LVC273DB,118
74LVC2G74 - Single D-type flip-flop with set and reset; positive edge trigger -- 74LVC2G74GF,115
74LVC2G74 - Single D-type flip-flop with set and reset; positive edge trigger -- 74LVC2G74GM,125
74LVC374A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state -- 74LVC374ADB,112
74LVC374A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state -- 74LVC374ADB,118
74LVC377 - Octal D-type flip-flop with data enable; positive-edge trigger -- 74LVC377DB,112
74LVC377 - Octal D-type flip-flop with data enable; positive-edge trigger -- 74LVC377DB,118
74LVC574A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger (3-state) -- 74LVC574ADB,112
74LVC574A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger (3-state) -- 74LVC574ADB,118
74LVC74A - Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LVC74ADB,112
74LVC74A - Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LVC74ADB,118
74LVCH162374A - 16-bit edge-triggered D-type flip-flop -- 74LVCH162374ADL,11
74LVCH162374A - 16-bit edge-triggered D-type flip-flop -- 74LVCH162374ADL:11
74LVT16374A; 74LVTH16374A - 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state -- 74LVT16374ADL,118
Product Status: Released for supply
Dual D-type flip-flop -- 74ABT74D,112
Dual D-type flip-flop -- 74ABT74D,118
Dual D-type flip-flop -- 74ABT74PW,118
The 74ABT74 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT74 is a dual positive edge-triggered D-type flip-flop featuring individual...
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHC74BQ-Q100X
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHC74D-Q100J
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHC74PW-Q100J
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHCT74BQ-Q100X
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHCT74D-Q100J
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHCT74PW-Q100J
The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74-Q100;
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHC74BQ,115
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHC74D,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHC74D,118
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHC74PW,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHC74PW,118
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHCT74BQ,115
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHCT74D,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHCT74D,118
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHCT74PW,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74AHCT74PW,118
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74;
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74ALVC74BQ,115
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74ALVC74D,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74ALVC74D,118
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74ALVC74PW,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74ALVC74PW,118
The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and...
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state -- 74ALVCH16374DGG:11
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state -- 74ALVCH16374DGG;11
The 74ALVCH16374 is 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for...
20-bit bus-interface D-type flip-flop' positive-edge trigger (3-State) -- 74ALVCH16821DGGS
20-bit bus-interface D-type flip-flop' positive-edge trigger (3-State) -- 74ALVCH16821DGGY
The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP)...
18-bit bus-interface D-type flip-flop with reset and enable; 3-state -- 74ALVCH16823DGGS
18-bit bus-interface D-type flip-flop with reset and enable; 3-state -- 74ALVCH16823DGGY
The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for...
2.5 V / 3.3 V 20-bit bus-interface D-type flip-flop, positive-edge trigger with 30 Ohm termination resistors (3-State) -- 74ALVT162821DGGS
2.5 V / 3.3 V 20-bit bus-interface D-type flip-flop, positive-edge trigger with 30 Ohm termination resistors (3-State) -- 74ALVT162821DGGY
2.5 V / 3.3 V 20-bit bus-interface D-type flip-flop, positive-edge trigger with 30 Ohm termination resistors (3-State) -- 74ALVT162821DL,512
2.5 V / 3.3 V 20-bit bus-interface D-type flip-flop, positive-edge trigger with 30 Ohm termination resistors (3-State) -- 74ALVT162821DL,518
The 74ALVT162821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC operation at 2.5V or 3.3V...
18-bit bus-interface D-type flip-flop -- 74ALVT162823DGGS
18-bit bus-interface D-type flip-flop -- 74ALVT162823DGGY
The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of...
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state -- 74ALVT16821DGGS
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state -- 74ALVT16821DGGY
The 74ALVT16821 high-performance Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC...
18-bit bus-interface D-type flip-flop with reset and enable; 3-state -- 74ALVT16823DGGS
18-bit bus-interface D-type flip-flop with reset and enable; 3-state -- 74ALVT16823DGGY
18-bit bus-interface D-type flip-flop with reset and enable; 3-state -- 74ALVT16823DL,512
18-bit bus-interface D-type flip-flop with reset and enable; 3-state -- 74ALVT16823DL,518
The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying...
Low-power D-type flip-flop with reset; positive-edge trigger -- 74AUP1G175GM,115
Low-power D-type flip-flop with reset; positive-edge trigger -- 74AUP1G175GM,132
Low-power D-type flip-flop with reset; positive-edge trigger -- 74AUP1G175GN,132
Low-power D-type flip-flop with reset; positive-edge trigger -- 74AUP1G175GS,132
Low-power D-type flip-flop with reset; positive-edge trigger -- 74AUP1G175GW,125
The 74AUP1G175 provides a low-power, low-voltage positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is...
Low-power D-type flip-flop with reset; positive-edge trigger -- 74AUP1G175GW-Q100H The 74AUP1G175-Q100 provides a low-power, low-voltage positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is...
Low-power D-type flip-flop; positive-edge trigger; 3-state -- 74AUP1G374GM,115
Low-power D-type flip-flop; positive-edge trigger; 3-state -- 74AUP1G374GM,132
Low-power D-type flip-flop; positive-edge trigger; 3-state -- 74AUP1G374GN,132
Low-power D-type flip-flop; positive-edge trigger; 3-state -- 74AUP1G374GS,132
Low-power D-type flip-flop; positive-edge trigger; 3-state -- 74AUP1G374GW,125
The 74AUP1G374 provides the single D-type flip-flop with 3-state output. The flip-flop will store the state of data input (D) that meet the set-up and hold times requirements on the...
Low-power D-type flip-flop; positive-edge trigger; 3-state -- 74AUP1G374GW-Q100H The 74AUP1G374-Q100 provides the single D-type flip-flop with 3-state output. The flip-flop stores the state of data input (D) that meets the set-up and hold times requirements on the LOW-to-HIGH...
Low-power D-type flip-flop with set and reset; positive-edge trigger -- 74AUP1G74DC,125
Low-power D-type flip-flop with set and reset; positive-edge trigger -- 74AUP1G74GN,115
Low-power D-type flip-flop with set and reset; positive-edge trigger -- 74AUP1G74GS,115
Low-power D-type flip-flop with set and reset; positive-edge trigger -- 74AUP1G74GT,115
Low-power D-type flip-flop with set and reset; positive-edge trigger -- 74AUP1G74GXX
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The...
Low-power D-type flip-flop with set and reset; positive-edge trigger -- 74AUP1G74DC-Q100H The 74AUP1G74-Q100 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The...
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G79GM,115
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G79GM,132
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G79GN,132
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G79GS,132
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G79GV,125
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G79GW,125
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G79GX,125
The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D...
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G80GM,115
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G80GM,132
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G80GN,132
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G80GS,132
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G80GW,125
Low-power D-type flip-flop; positive-edge trigger -- 74AUP1G80GX,125
The 74AUP1G80 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input...
Low-power dual D-type flip-flop; positive-edge trigger -- 74AUP2G79DC,125
Low-power dual D-type flip-flop; positive-edge trigger -- 74AUP2G79GN,115
Low-power dual D-type flip-flop; positive-edge trigger -- 74AUP2G79GS,115
Low-power dual D-type flip-flop; positive-edge trigger -- 74AUP2G79GT,115
The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP).
Low-power dual D-type flip-flop; positive-edge trigger -- 74AUP2G79DC-Q100H The 74AUP2G79-Q100 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP).
Low-power dual D-type flip-flop; positive-edge trigger -- 74AUP2G80DC,125
Low-power dual D-type flip-flop; positive-edge trigger -- 74AUP2G80GN,115
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input...
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state -- 74AVC16374DGG,112
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state -- 74AVC16374DGG,118
The 74AVC16374 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The 74AVC16374 consist of 2 sections of 8 edge-triggered...
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state -- 74AVC16374DGG-Q10J The 74AVC16374-Q100 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The 74AVC16374-Q100 consist of 2 sections of 8 edge-triggered...
Dual JK flip-flop with reset; negative-edge trigger -- 74HC107D-Q100J
Dual JK flip-flop with reset; negative-edge trigger -- 74HC107PW-Q100J
Dual JK flip-flop with reset; negative-edge trigger -- 74HCT107D-Q100J
The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip‑flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The...
Dual JK flip-flop with reset; negative-edge trigger -- 74HC107D,652
Dual JK flip-flop with reset; negative-edge trigger -- 74HC107D,653
Dual JK flip-flop with reset; negative-edge trigger -- 74HC107PW,112
Dual JK flip-flop with reset; negative-edge trigger -- 74HC107PW,118
Dual JK flip-flop with reset; negative-edge trigger -- 74HCT107D,652
Dual JK flip-flop with reset; negative-edge trigger -- 74HCT107D,653
The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The...
Dual JK flip-flop with set and reset; positive-edge-trigger -- 74HC109D-Q100J
Dual JK flip-flop with set and reset; positive-edge-trigger -- 74HCT109D-Q100J
The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary...
Dual JK flip-flop with set and reset; positive-edge trigger -- 74HC109D,652
Dual JK flip-flop with set and reset; positive-edge trigger -- 74HC109D,653
Dual JK flip-flop with set and reset; positive-edge trigger -- 74HCT109D,652
Dual JK flip-flop with set and reset; positive-edge trigger -- 74HCT109D,653
Dual JK flip-flop with set and reset; positive-edge trigger -- 74HCT109PW,112
Dual JK flip-flop with set and reset; positive-edge trigger -- 74HCT109PW,118
The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary...
dual JK flip-flop with set and reset; negative-edge trigger -- 74HC112D,652
dual JK flip-flop with set and reset; negative-edge trigger -- 74HC112D,653
dual JK flip-flop with set and reset; negative-edge trigger -- 74HC112PW,112
dual JK flip-flop with set and reset; negative-edge trigger -- 74HC112PW,118
dual JK flip-flop with set and reset; negative-edge trigger -- 74HCT112D,652
dual JK flip-flop with set and reset; negative-edge trigger -- 74HCT112D,653
dual JK flip-flop with set and reset; negative-edge trigger -- 74HCT112PW,112
dual JK flip-flop with set and reset; negative-edge trigger -- 74HCT112PW,118
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ...
Hex D-type flip-flop with reset; positive-edge trigger -- 74HC174D-Q100J
Hex D-type flip-flop with reset; positive-edge trigger -- 74HC174PW-Q100J
Hex D-type flip-flop with reset; positive-edge trigger -- 74HCT174D-Q100J
Hex D-type flip-flop with reset; positive-edge trigger -- 74HCT174PW-Q100J
The 74HC174-Q100; 74HCT174-Q100 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all...
Hex D-type flip-flop with reset; positive-edge trigger -- 74HC174D,652
Hex D-type flip-flop with reset; positive-edge trigger -- 74HC174D,653
Hex D-type flip-flop with reset; positive-edge trigger -- 74HC174PW,112
Hex D-type flip-flop with reset; positive-edge trigger -- 74HC174PW,118
Hex D-type flip-flop with reset; positive-edge trigger -- 74HCT174D,652
Hex D-type flip-flop with reset; positive-edge trigger -- 74HCT174D,653
Hex D-type flip-flop with reset; positive-edge trigger -- 74HCT174PW,118
The 74HC174; 74HCT174 are hex positive edge -triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR ) inputs load and...
Dual JK flip-flop with reset; negative-edge trigger -- 74HC73D,652
Dual JK flip-flop with reset; negative-edge trigger -- 74HC73D,653
Dual JK flip-flop with reset; negative-edge trigger -- 74HC73PW,112
Dual JK flip-flop with reset; negative-edge trigger -- 74HC73PW,118
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K...
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HC74BQ,115
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HC74D,652
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HC74D,653
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HC74PW,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HC74PW,118
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HCT74BQ,115
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HCT74D,652
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HCT74D,653
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HCT74PW,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74HCT74PW,118
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs.
Dual D-type flip-flop with set and reset; positive edge-trigger -- 74HC74BQ-Q100,115
Dual D-type flip-flop with set and reset; positive edge-trigger -- 74HC74D-Q100,118
Dual D-type flip-flop with set and reset; positive edge-trigger -- 74HC74PW-Q100,118
Dual D-type flip-flop with set and reset; positive edge-trigger -- 74HCT74BQ-Q100,115
Dual D-type flip-flop with set and reset; positive edge-trigger -- 74HCT74D-Q100,118
Dual D-type flip-flop with set and reset; positive edge-trigger -- 74HCT74PW-Q100,118
The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at...
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LV74D,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LV74D,118
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LV74PW,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LV74PW,118
The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LV74D-Q100J
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LV74PW-Q100J
The 74LV74-Q100 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state -- 74LVC16374ADGG,112
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state -- 74LVC16374ADGG,118
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state -- 74LVCH16374ADGG,11
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state -- 74LVCH16374ADGG:11
The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus oriented applications. It consists of...
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state -- 74LVC16374ADGG-Q1J
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state -- 74LVCH16374ADGG-QJ
The 74LVC16374A-Q100 and 74LVCH16374A-Q100 are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A-Q100 only) for each flip-flop and 3-state outputs for bus-oriented applications. It consists of two...
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LVC74ABQ,115
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LVC74AD,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LVC74AD,118
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LVC74APW,112
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LVC74APW,118
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set...
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LVC74ABQ-Q100X
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LVC74AD-Q100J
Dual D-type flip-flop with set and reset; positive-edge trigger -- 74LVC74APW-Q100J
The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The...
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state -- 74LVC823ABQ,118
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state -- 74LVC823AD,118
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state -- 74LVC823APW,112
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state -- 74LVC823APW,118
The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops stores...
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive -- 74LVC823ABQ-Q100J The 74LVC823A-Q100 is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9...
16-bit edge-triggered D-type flip-flop -- 74LVCH162374ADGG,1
16-bit edge-triggered D-type flip-flop -- 74LVCH162374ADGG:1
The 74LVCH162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The device consists of two sections of 8 edge-triggered...
3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ohm termination resistors; 3-state -- 74LVT162374DGG,112
3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ohm termination resistors; 3-state -- 74LVT162374DGG,118
The 74LVT162374 is a high performance BiCMOS product designed for VCC operation at 3.3 V. The 74LVT162374 is designed with 30 Ω series resistance in both the HIGH and...
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state -- 74LVT16374ADGG,112
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state -- 74LVT16374ADGG,118
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state -- 74LVTH16374ADGG,18
The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for VCC operation at 3.3 V. This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The device...
Dual D-type flip-flop -- HEF4013BT,652
Dual D-type flip-flop -- HEF4013BT,653
Dual D-type flip-flop -- HEF4013BTT,112
Dual D-type flip-flop -- HEF4013BTT,118
The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW...
Dual D-type flip-flop -- HEF4013BT-Q100J
Dual D-type flip-flop -- HEF4013BTT-Q100J
The HEF4013B-Q100 is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW...
Dual JK flip-flop -- HEF4027BT,652
Dual JK flip-flop -- HEF4027BT,653
The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and...
Dual JK flip-flop -- HEF4027BT-Q100J The HEF4027B-Q100 is an edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and...

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