Nexperia B.V. 18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state 74ALVT162823DGG,11

The 74ALVT162823 is an 18-bit positive-edge triggered D-type flip-flop with 30 Ω termination resistors, 3-state outputs reset and enable.

The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling 9-bits. When nCE is LOW, the flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. A LOW on nMR will reset the flip-flops LOW. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs.

Features and benefits

• Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
• 5 V I/O compatible
• Ideal where high speed, light loading or increased fan-in are required with MOS microprocessors
• Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• Live insertion and extraction permitted
• Power-up 3-state
• Power-up reset
• Output capability: +12 mA to −12 mA
• Outputs include series resistance of 30 Ω making external termination resistors unnecessary
• Latch-up protection:
• JESD78: exceeds 500 mA
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +85 °C

74ALVT162823 - 18-bit bus-interface D-type flip-flop

Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240", 6.10mm Width)