Nexperia B.V. Dual D-type flip-flop with set and reset; positive-edge trigger 74ALVC74PW,118

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Dual D-type flip-flop with set and reset; positive-edge trigger - 74ALVC74PW,118 - Nexperia B.V.
Nijmegen, Netherlands
Dual D-type flip-flop with set and reset; positive-edge trigger
74ALVC74PW,118
Dual D-type flip-flop with set and reset; positive-edge trigger 74ALVC74PW,118
The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B (2.7 to 3.6 V) 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA ESD protection: MM JESD22-A115-A exceeds 200 V HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1 kV ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C

The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.

The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features and benefits

  • Wide supply voltage range from 1.65 V to 3.6 V
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 to 1.95 V)
    • JESD8-5 (2.3 to 2.7 V)
    • JESD8B (2.7 to 3.6 V)
  • 3.6 V tolerant inputs/outputs
  • CMOS low power consumption
  • Direct interface with TTL levels (2.7 V to 3.6 V)
  • Power-down mode
  • Latch-up performance exceeds 250 mA
  • ESD protection:
    • MM JESD22-A115-A exceeds 200 V
    • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
    • CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1 kV
  • ESD protection:
    • HBM JESD22-A114E exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Specified from -40 °C to +85 °C
Supplier's Site Datasheet
Logic - Flip Flops - 74ALVC74PW,118 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74ALVC74PW,118
Logic - Flip Flops 74ALVC74PW,118
IC FF D-TYPE DUAL 1BIT 14TSSOP

IC FF D-TYPE DUAL 1BIT 14TSSOP

Supplier's Site Datasheet
Yishun, Singapore
Logic - Logic - Flip Flops - 74ALVC74PW,118
1007675-74ALVC74PW,118
Logic - Logic - Flip Flops - 74ALVC74PW,118 1007675-74ALVC74PW,118
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1007675-74ALVC74PW,1 18 Packaging: Reel - TR Type: D-Type Mounting: SMD (SMT) Output Type: Differential Current - Output High, Low: 24mA, 24mA Number of Elements: 2 Number of Bits per Element: 1 Max Propagation Delay @ V, Max CL: 3.8ns @ 3.3V, 50pF Trigger Type: Positive Edge Current - Quiescent: 10μA Input Capacitance: 3.5pF Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 85°C (TA) Dimension: 14-TSSOP (0.173", 4.40mm Width) Purpose: Set(Preset) and Reset Supply Voltage - Operating: 1.65 V to 3.6 V Max Frequency: 425MHz Popularity: Medium Fake Threat In the Open Market: 38 pct. Supply and Demand Status: Sufficient

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1007675-74ALVC74PW,118
Packaging: Reel - TR
Type: D-Type
Mounting: SMD (SMT)
Output Type: Differential
Current - Output High, Low: 24mA, 24mA
Number of Elements: 2
Number of Bits per Element: 1
Max Propagation Delay @ V, Max CL: 3.8ns @ 3.3V, 50pF
Trigger Type: Positive Edge
Current - Quiescent: 10μA
Input Capacitance: 3.5pF
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 85°C (TA)
Dimension: 14-TSSOP (0.173", 4.40mm Width)
Purpose: Set(Preset) and Reset
Supply Voltage - Operating: 1.65 V to 3.6 V
Max Frequency: 425MHz
Popularity: Medium
Fake Threat In the Open Market: 38 pct.
Supply and Demand Status: Sufficient

Supplier's Site Datasheet
Flip Flops - 74ALVC74PW,118-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE DUAL 1BIT 14TSSOP

IC FF D-TYPE DUAL 1BIT 14TSSOP

Supplier's Site Datasheet
 - 74ALVC74PW,118 - Rochester Electronics
Newburyport, MA, United States
Nexperia 74ALVC74PW - D Flip-Flop, ALVC/VCX/A Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, TSSOP14

Nexperia 74ALVC74PW - D Flip-Flop, ALVC/VCX/A Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, TSSOP14

Supplier's Site Datasheet
Flip Flop, D, -40 To 85Deg C Rohs Compliant Nexperia - 74AH2239 - Newark, An Avnet Company
Chicago, IL, United States
Flip Flop, D, -40 To 85Deg C Rohs Compliant Nexperia
74AH2239
Flip Flop, D, -40 To 85Deg C Rohs Compliant Nexperia 74AH2239
FLIP FLOP, D, -40 TO 85DEG C ROHS COMPLIANT: YES

FLIP FLOP, D, -40 TO 85DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Lingto Electronic Limited Win Source Electronics DigiKey Rochester Electronics Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74ALVC74PW,118 74ALVC74PW,118 1007675-74ALVC74PW,118 74ALVC74PW,118-ND 74ALVC74PW,118 74AH2239
Product Name Dual D-type flip-flop with set and reset; positive-edge trigger Logic - Flip Flops Logic - Logic - Flip Flops - 74ALVC74PW,118 Flip Flops Flip Flop, D, -40 To 85Deg C Rohs Compliant Nexperia
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered; Positive Edge Positive-edge Triggered Positive-edge Triggered
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 1.65 - 3.6 1.65 V ~ 3.6 V 1.65V ~ 3.6V
Features ESD Protection
Propagation Delay 2.3 ns 3.8 ns 3.8 ns
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