Nexperia B.V. Low-power D-type flip-flop; positive-edge trigger; 3-state 74AUP1G374GN,132

The 74AUP1G374 is a single D-type flip-flop; positive-edge trigger (3-state). Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 0.8 V to 3.6 V
• High noise immunity
• CMOS low power dissipation
• Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V)
• JESD8-11 (0.9 V to 1.65 V)
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F Class 3A. Exceeds 5000 V
• MM JESD22-A115-A exceeds 200 V
• CDM JESD22-C101E exceeds 1000 V
• Low static power consumption; I_CC = 0.9 μA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Overvoltage tolerant inputs to 3.6 V
• Low noise overshoot and undershoot < 10 % of V_CC
• I_OFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G374 - Low-power D-type flip-flop; positive-edge trigger, 3-state

IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON