The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
IC FF JK TYPE DUAL 1BIT 14SO
FLIP FLOP, JK, -40 TO 125DEG C ROHS COMPLIANT: YES
|Nexperia B.V.||Lingto Electronic Limited||Newark, An Avnet Company|
|Product Name||Dual JK flip-flop with reset; negative-edge trigger||Logic - Flip Flops||Flip Flop, Jk, -40 To 125Deg C Rohs Compliant Nexperia|
|Supply Voltage||2.5V; 3V; 3.3V; 3.6V; 5V; 2.0 - 6.0|
|Propagation Delay||16 ns|