Nexperia B.V. Dual D-type flip-flop with set and reset; positive-edge trigger 74ALVC74D,112

Description
The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V CMOS low power dissipation Overvoltage tolerant inputs to 3.6 V Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA per JESD78 Class II.A Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Dual D-type flip-flop with set and reset; positive-edge trigger - 74ALVC74D,112 - Nexperia B.V.
    Nexperia B.V.
  • Flip Flops - 1727-6097-ND - DigiKey
    DigiKey
  • Integrated Circuits (ICs) - Logic - Flip Flops - 74ALVC74D,112 - Shenzhen Shengyu Electronics Technology Limited
    Shenzhen Shengyu Electronics Technology Limited
  • Flip Flops - 74ALVC74D,112 - Quarktwin Technology Ltd.
    Quarktwin Technology Ltd.
Request a Quote Datasheet
Description
The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V CMOS low power dissipation Overvoltage tolerant inputs to 3.6 V Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA per JESD78 Class II.A Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Dual D-type flip-flop with set and reset; positive-edge trigger - 74ALVC74D,112 - Nexperia B.V.
Nexperia B.V.
Nijmegen, Netherlands
Dual D-type flip-flop with set and reset; positive-edge trigger
74ALVC74D,112
Dual D-type flip-flop with set and reset; positive-edge trigger 74ALVC74D,112
The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V CMOS low power dissipation Overvoltage tolerant inputs to 3.6 V Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA per JESD78 Class II.A Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.

Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 3.6 V
  • CMOS low power dissipation
  • Overvoltage tolerant inputs to 3.6 V
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD78 Class II.A
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 to 1.95 V)
    • JESD8-5 (2.3 to 2.7 V)
    • JESD8C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 1727-6097-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6097-ND
Flip Flops 1727-6097-ND
"Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154"", 3.90mm Width)"

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154"", 3.90mm Width)"

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74ALVC74D,112 - Shenzhen Shengyu Electronics Technology Limited
Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74ALVC74D,112
Integrated Circuits (ICs) - Logic - Flip Flops 74ALVC74D,112
IC FF D-TYPE DUAL 1BIT 14SO

IC FF D-TYPE DUAL 1BIT 14SO

Supplier's Site
Flip Flops - 74ALVC74D,112 - Quarktwin Technology Ltd.
Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74ALVC74D,112
Flip Flops 74ALVC74D,112
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154", 3.90mm Width)

Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154", 3.90mm Width)

Buy Now Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Shenzhen Shengyu Electronics Technology Limited Quarktwin Technology Ltd.
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74ALVC74D,112 1727-6097-ND 74ALVC74D,112 74ALVC74D,112
Product Name Dual D-type flip-flop with set and reset; positive-edge trigger Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Flip Flops
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 1.65 - 3.6 1.65V ~ 3.6V 3.6V; 1.65V ~ 3.6V
Features ESD Protection
Propagation Delay 2.3 ns 3.8 ns
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