The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q).
The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
IC FF D-TYPE DUAL 1BIT 14DHVQFN
IC FF D-TYPE DUAL 1BIT 14DHVQFN
IC FF D-TYPE DUAL 1BIT 14DHVQFN
IC FF D-TYPE DUAL 1BIT 14DHVQFN
| Nexperia B.V. | Lingto Electronic Limited | DigiKey | |
|---|---|---|---|
| Product Category | Flip-Flops | Flip-Flops | Flip-Flops |
| Product Number | 74AHC74BQ-Q100X | 74AHC74BQ-Q100X | 1727-74AHC74BQ-Q100XCT-ND |
| Product Name | Dual D-type flip-flop with set and reset; positive-edge trigger | Logic - Flip Flops | Flip Flops |
| Flip-Flop Type | D | D | |
| Triggering | Positive-edge Triggered | Positive-edge Triggered | |
| Supply Voltage | 2.5V; 3V; 3.3V; 3.6V; 5V; 2.0 - 5.5 | 2V ~ 5.5V | |
| Features | ESD Protection | ||
| Propagation Delay | 3.7 ns | 9.3 ns |
