Nexperia B.V. Datasheets for Logic Decoders and Demultiplexers

Logic decoders and logic demultiplexers move data between inputs and outputs. In the case of digital decoders, the coded information is translated into familiar or uncoded formats, while digital multiplexers transmit data from one input through to several output lines. 
Logic Decoders and Demultiplexers: Learn more

Product Name Notes
3-to-8 line decoder, demultiplexer with address latches -- 74HC237D-Q100J Features Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Combines 3-to-8 decoder with 3-bit latch...
74AUP1G18 - Low-power 1-of-2 demultiplexer with 3-state deselected output -- 74AUP1G18GF,132
74AUP1G19 - Low-power 1-of-2 decoder/demultiplexer -- 74AUP1G19GF,132
74HC(T)138 - 3-to-8 line decoder/demultiplexer; inverting -- 74HC138DB,112
74HC(T)138 - 3-to-8 line decoder/demultiplexer; inverting -- 74HC138DB,118
74HC(T)138 - 3-to-8 line decoder/demultiplexer; inverting -- 74HCT138DB,112
74HC(T)138 - 3-to-8 line decoder/demultiplexer; inverting -- 74HCT138DB,118
74HC(T)139 - Dual 2-to-4 line decoder/demultiplexer -- 74HC139DB,112
74HC(T)139 - Dual 2-to-4 line decoder/demultiplexer -- 74HC139DB,118
74HC(T)139 - Dual 2-to-4 line decoder/demultiplexer -- 74HCT139DB,112
74HC(T)139 - Dual 2-to-4 line decoder/demultiplexer -- 74HCT139DB,118
74HC(T)139-Q100 - Dual 2-to-4 line decoder/demultiplexer -- 74HC139DB-Q100J
74HC(T)139-Q100 - Dual 2-to-4 line decoder/demultiplexer -- 74HCT139DB-Q100J
74HC(T)154 - 4-to-16 line decoder/demultiplexer -- 74HC154DB,112
74HC(T)154 - 4-to-16 line decoder/demultiplexer -- 74HC154DB,118
74HC(T)154 - 4-to-16 line decoder/demultiplexer -- 74HCT154DB,112
74HC(T)154 - 4-to-16 line decoder/demultiplexer -- 74HCT154DB,118
74HC(T)238 - 3-to-8 line decoder/demultiplexer -- 74HC238DB,112
74HC(T)238 - 3-to-8 line decoder/demultiplexer -- 74HC238DB,118
74HC(T)238 - 3-to-8 line decoder/demultiplexer -- 74HCT238DB,112
74HC(T)238 - 3-to-8 line decoder/demultiplexer -- 74HCT238DB,118
74HC(T)4514 - 4-to-16 line decoder/demultiplexer with input latches -- 74HC4514DB,112
74HC(T)4514 - 4-to-16 line decoder/demultiplexer with input latches -- 74HC4514DB,118
74HC137 - 3-to-8 line decoder, demultiplexer with address latches; inverting -- 74HC137DB,112
74HC137 - 3-to-8 line decoder, demultiplexer with address latches; inverting -- 74HC137DB,118
74HC237 - 3-to-8 line decoder, demultiplexer with address latches -- 74HC237DB,112
74HC237 - 3-to-8 line decoder, demultiplexer with address latches -- 74HC237DB,118
74LV138 - 3-to-8 line decoder/demultplexer; inverting -- 74LV138DB,112
74LV138 - 3-to-8 line decoder/demultplexer; inverting -- 74LV138DB,118
74LVC138A - 3-to-8 line decoder/demultiplexer; inverting -- 74LVC138ADB,112
74LVC138A - 3-to-8 line decoder/demultiplexer; inverting -- 74LVC138ADB,118
74LVC139 - Dual 2-to-4 line decoder/demultiplexer -- 74LVC139DB,118
74LVC1G19 - 1-of-2 decoder/demultiplexer -- 74LVC1G19GF,132
Product Status: Released for supply
3-to-8 line decoder/demultiplexer; inverting -- 74AHC138BQ-Q100X
3-to-8 line decoder/demultiplexer; inverting -- 74AHC138D-Q100J
3-to-8 line decoder/demultiplexer; inverting -- 74AHC138PW-Q100J
3-to-8 line decoder/demultiplexer; inverting -- 74AHCT138BQ-Q100X
3-to-8 line decoder/demultiplexer; inverting -- 74AHCT138D-Q100J
3-to-8 line decoder/demultiplexer; inverting -- 74AHCT138PW-Q100J
The 74AHC138-Q100; 74AHCT138-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138-Q100; 74AHCT138-Q100...
3-to-8 line decoder/demultiplexer; inverting -- 74AHC138BQ,115
3-to-8 line decoder/demultiplexer; inverting -- 74AHC138D,112
3-to-8 line decoder/demultiplexer; inverting -- 74AHC138D,118
3-to-8 line decoder/demultiplexer; inverting -- 74AHC138PW,112
3-to-8 line decoder/demultiplexer; inverting -- 74AHC138PW,118
3-to-8 line decoder/demultiplexer; inverting -- 74AHCT138BQ,115
3-to-8 line decoder/demultiplexer; inverting -- 74AHCT138D,112
3-to-8 line decoder/demultiplexer; inverting -- 74AHCT138D,118
3-to-8 line decoder/demultiplexer; inverting -- 74AHCT138PW,112
3-to-8 line decoder/demultiplexer; inverting -- 74AHCT138PW,118
The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138;
Dual 2-to-4 line decoder/demultiplexer -- 74AHC139D-Q100J
Dual 2-to-4 line decoder/demultiplexer -- 74AHC139PW-Q100J
Dual 2-to-4 line decoder/demultiplexer -- 74AHCT139D-Q100J
Dual 2-to-4 line decoder/demultiplexer -- 74AHCT139PW-Q100J
The 74AHC139-Q100; 74AHCT139-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC139-Q100;
Dual 2-to-4 line decoder/demultiplexer -- 74AHC139D,112
Dual 2-to-4 line decoder/demultiplexer -- 74AHC139D,118
Dual 2-to-4 line decoder/demultiplexer -- 74AHC139PW,112
Dual 2-to-4 line decoder/demultiplexer -- 74AHC139PW,118
Dual 2-to-4 line decoder/demultiplexer -- 74AHCT139D,118
Dual 2-to-4 line decoder/demultiplexer -- 74AHCT139PW,112
Dual 2-to-4 line decoder/demultiplexer -- 74AHCT139PW,118
The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC139;
Low-power 1-of-2 demultiplexer with 3-state deselected output -- 74AUP1G18GM,115
Low-power 1-of-2 demultiplexer with 3-state deselected output -- 74AUP1G18GM,132
Low-power 1-of-2 demultiplexer with 3-state deselected output -- 74AUP1G18GN,132
Low-power 1-of-2 demultiplexer with 3-state deselected output -- 74AUP1G18GS,132
Low-power 1-of-2 demultiplexer with 3-state deselected output -- 74AUP1G18GW,125
The 74AUP1G18 provides a 1-of-2 non-inverting demultiplexer with 3-state output. The 74AUP1G18 buffers the data on input pin (A) and passes it either to output 1Y or 2Y, depending on...
Low-power 1-of-2 decoder/demultiplexer -- 74AUP1G19GM,115
Low-power 1-of-2 decoder/demultiplexer -- 74AUP1G19GM,132
Low-power 1-of-2 decoder/demultiplexer -- 74AUP1G19GN,132
Low-power 1-of-2 decoder/demultiplexer -- 74AUP1G19GS,132
Low-power 1-of-2 decoder/demultiplexer -- 74AUP1G19GW,125
The 74AUP1G19 provides a 1-of-2 decoder/demultiplexer with a common output enable. It buffers the data on input pin A and passes it either to output pin 1Y (true) or 2Y...
3-to-8 line decoder, demultiplexer with address latches; inverting -- 74HC137D,652
3-to-8 line decoder, demultiplexer with address latches; inverting -- 74HC137D,653
The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC standard no. 7A. The...
3-to-8 line decoder/demultiplexer; inverting -- 74HC138BQ-Q100,115
3-to-8 line decoder/demultiplexer; inverting -- 74HC138D-Q100,118
3-to-8 line decoder/demultiplexer; inverting -- 74HC138PW-Q100,118
3-to-8 line decoder/demultiplexer; inverting -- 74HCT138BQ-Q100,11
3-to-8 line decoder/demultiplexer; inverting -- 74HCT138D-Q100,118
3-to-8 line decoder/demultiplexer; inverting -- 74HCT138PW-Q100,11
The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and...
3-to-8 line decoder/demultiplexer; inverting -- 74HC138BQ,115
3-to-8 line decoder/demultiplexer; inverting -- 74HC138D,652
3-to-8 line decoder/demultiplexer; inverting -- 74HC138D,653
3-to-8 line decoder/demultiplexer; inverting -- 74HC138PW,112
3-to-8 line decoder/demultiplexer; inverting -- 74HC138PW,118
3-to-8 line decoder/demultiplexer; inverting -- 74HCT138BQ,115
3-to-8 line decoder/demultiplexer; inverting -- 74HCT138D,652
3-to-8 line decoder/demultiplexer; inverting -- 74HCT138D,653
3-to-8 line decoder/demultiplexer; inverting -- 74HCT138PW,112
3-to-8 line decoder/demultiplexer; inverting -- 74HCT138PW,118
The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and...
Dual 2-to-4 line decoder/demultiplexer -- 74HC139D-Q100J
Dual 2-to-4 line decoder/demultiplexer -- 74HC139PW-Q100J
Dual 2-to-4 line decoder/demultiplexer -- 74HCT139D-Q100J
Dual 2-to-4 line decoder/demultiplexer -- 74HCT139PW-Q100J
The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH...
Dual 2-to-4 line decoder/demultiplexer -- 74HC139D,652
Dual 2-to-4 line decoder/demultiplexer -- 74HC139D,653
Dual 2-to-4 line decoder/demultiplexer -- 74HC139PW,112
Dual 2-to-4 line decoder/demultiplexer -- 74HC139PW,118
Dual 2-to-4 line decoder/demultiplexer -- 74HCT139D,652
Dual 2-to-4 line decoder/demultiplexer -- 74HCT139D,653
Dual 2-to-4 line decoder/demultiplexer -- 74HCT139PW,112
Dual 2-to-4 line decoder/demultiplexer -- 74HCT139PW,118
The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH...
4-to-16 line decoder/demultiplexer -- 74HC154BQ,118
4-to-16 line decoder/demultiplexer -- 74HC154D,652
4-to-16 line decoder/demultiplexer -- 74HC154D,653
4-to-16 line decoder/demultiplexer -- 74HC154PW,112
4-to-16 line decoder/demultiplexer -- 74HC154PW,118
4-to-16 line decoder/demultiplexer -- 74HCT154BQ,118
4-to-16 line decoder/demultiplexer -- 74HCT154D,652
4-to-16 line decoder/demultiplexer -- 74HCT154D,653
4-to-16 line decoder/demultiplexer -- 74HCT154PW,112
4-to-16 line decoder/demultiplexer -- 74HCT154PW,118
The 74HC154; 74HCT154 is a 4-to-16 line decoder/demultiplexer. It decodes four binary weighted address inputs (A0 to A3) to sixteen mutually exclusive outputs (Y0 to Y15). The device features two...
3-to-8 line decoder, demultiplexer with address latches -- 74HC237D,652
3-to-8 line decoder, demultiplexer with address latches -- 74HC237D,653
The 74HC237 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC237 is specified in compliance with JEDEC standard no. 7A. The 74HC237...
3-to-8 line decoder/demultiplexer -- 74HC238BQ,115
3-to-8 line decoder/demultiplexer -- 74HC238D,652
3-to-8 line decoder/demultiplexer -- 74HC238D,653
3-to-8 line decoder/demultiplexer -- 74HC238PW,112
3-to-8 line decoder/demultiplexer -- 74HC238PW,118
3-to-8 line decoder/demultiplexer -- 74HCT238BQ,115
3-to-8 line decoder/demultiplexer -- 74HCT238D,652
3-to-8 line decoder/demultiplexer -- 74HCT238D,653
3-to-8 line decoder/demultiplexer -- 74HCT238PW,112
3-to-8 line decoder/demultiplexer -- 74HCT238PW,118
The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2...
BCD to decimal decoder (1-of-10) -- 74HC42D,652
BCD to decimal decoder (1-of-10) -- 74HC42D,653
The 74HC42 is a one of ten BCD to decimal decoder. It accepts four BCD inputs (0A to 3A) and provides ten mutually exclusive outputs (0Y to 9Y). The logic...
BCD to 7-segment latch/decoder/driver -- 74HC4511D,652
BCD to 7-segment latch/decoder/driver -- 74HC4511D,653
BCD to 7-segment latch/decoder/driver -- 74HCT4511D,652
BCD to 7-segment latch/decoder/driver -- 74HCT4511D,653
The 74HC4511; 74HCT4511 is a BCD to 7-segment latch/decoder/driver with four address inputs (A, B, C, D), a latch enable input (LE), a ripple blanking input (BI), a lamp test...
4-to-16 line decoder/demultiplexer with input latches -- 74HC4514D,652
4-to-16 line decoder/demultiplexer with input latches -- 74HC4514D,653
4-to-16 line decoder/demultiplexer with input latches -- 74HC4514PW,112
4-to-16 line decoder/demultiplexer with input latches -- 74HC4514PW,118
4-to-16 line decoder/demultiplexer with input latches -- 74HCT4514D,652
4-to-16 line decoder/demultiplexer with input latches -- 74HCT4514D,653
4-to-16 line decoder/demultiplexer with input latches -- 74HCT4514PW,112
4-to-16 line decoder/demultiplexer with input latches -- 74HCT4514PW,118
The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16...
4-to-16 line decoder/demultiplexer with input latches; inverting -- 74HC4515D,652
4-to-16 line decoder/demultiplexer with input latches; inverting -- 74HC4515D,653
The 74HC4515 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3) with latches, a latch enable input (LE), an enable input (E) and 16 inverting...
3-to-8 line decoder/demultiplexer -- 74HC238BQ-Q100X
3-to-8 line decoder/demultiplexer -- 74HC238D-Q100J
3-to-8 line decoder/demultiplexer -- 74HC238PW-Q100J
3-to-8 line decoder/demultiplexer -- 74HCT238BQ-Q100X
3-to-8 line decoder/demultiplexer -- 74HCT238D-Q100J
3-to-8 line decoder/demultiplexer -- 74HCT238PW-Q100J
The 74HC_HCT238-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3).
3-to-8 line decoder/demultplexer; inverting -- 74LV138BQ,115
3-to-8 line decoder/demultplexer; inverting -- 74LV138D,112
3-to-8 line decoder/demultplexer; inverting -- 74LV138D,118
3-to-8 line decoder/demultplexer; inverting -- 74LV138PW,112
3-to-8 line decoder/demultplexer; inverting -- 74LV138PW,118
The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted...
3-to-8 line decoder/demultiplexer; inverting -- 74LVC138ABQ,115
3-to-8 line decoder/demultiplexer; inverting -- 74LVC138AD,112
3-to-8 line decoder/demultiplexer; inverting -- 74LVC138AD,118
3-to-8 line decoder/demultiplexer; inverting -- 74LVC138APW,112
3-to-8 line decoder/demultiplexer; inverting -- 74LVC138APW,118
The 74LVC138A is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y0 to Y7) that...
3-to-8 line decoder/demultiplexer; inverting -- 74LVC138ABQ-Q100X
3-to-8 line decoder/demultiplexer; inverting -- 74LVC138AD-Q100J
3-to-8 line decoder/demultiplexer; inverting -- 74LVC138APW-Q100J
The 74LVC138A-Q100 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2). When the inputs are enabled, it provides eight mutually exclusive outputs (Y0...
Dual 2-to-4 line decoder/demultiplexer -- 74LVC139BQ,115
Dual 2-to-4 line decoder/demultiplexer -- 74LVC139D,112
Dual 2-to-4 line decoder/demultiplexer -- 74LVC139D,118
Dual 2-to-4 line decoder/demultiplexer -- 74LVC139PW,112
Dual 2-to-4 line decoder/demultiplexer -- 74LVC139PW,118
The 74LVC139 is a dual 2-to-4 line decoder/demultiplexer. It has two independent decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four mutually exclusive outputs (nY0 to...
1-of-2 non-inverting demultiplexer with 3-state deselected output -- 74LVC1G18GV,125
1-of-2 non-inverting demultiplexer with 3-state deselected output -- 74LVC1G18GW,125
The 74LVC1G18 is a 1-of-2 non-inverting demultiplexer with a 3-state output. The device buffers the data on input pin A and passes it either to output 1Y or 2Y, depending...
1-of-2 non-inverting demultiplexer with 3-state deselected output -- 74LVC1G18GV-Q100H
1-of-2 non-inverting demultiplexer with 3-state deselected output -- 74LVC1G18GW-Q100H
The 74LVC1G18-Q100 is a 1-of-2 non-inverting demultiplexer with a 3-state output. The device buffers the data on input pin A. It is passed to either output 1Y or 2Y, depending...
1-of-2 decoder/demultiplexer -- 74LVC1G19GM,115
1-of-2 decoder/demultiplexer -- 74LVC1G19GM,132
1-of-2 decoder/demultiplexer -- 74LVC1G19GN,132
1-of-2 decoder/demultiplexer -- 74LVC1G19GS,132
1-of-2 decoder/demultiplexer -- 74LVC1G19GV,125
1-of-2 decoder/demultiplexer -- 74LVC1G19GW,125
The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement)...
1-of-2 decoder/demultiplexer -- 74LVC1G19GW-Q100H The 74LVC1G19-Q100 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement)...
BCD to decimal decoder -- HEF4028BT,652
BCD to decimal decoder -- HEF4028BT,653
The HEF4028B is a 4-bit BCD to decimal decoder, a 4-bit BCO to octal decoder with active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer. The outputs are...
BCD to 7-segment latch/decoder/driver -- HEF4543BT,652
BCD to 7-segment latch/decoder/driver -- HEF4543BT,653
The HEF4543B is a BCD to 7-segment latch/decoder/driver for liquid crystal and LED displays. It has four address inputs (D0 to D3), an active LOW latch enable input (LE), an...
1-of-4 decoder/demultiplexer -- HEF4555BT,652
1-of-4 decoder/demultiplexer -- HEF4555BT,653
The HEF4555B contains two 1-of-4 decoders/demultiplexers. Each has two address inputs (nA0 and nA1, an active LOW enable input (nE) and four mutually exclusive outputs which are active HIGH (nY0...
1-of-4 decoder/demultiplexer -- HEF4555BT-Q100J The HEF4555B-Q100 contains two 1‑of‑4 decoders/demultiplexers. Each decoder/demultiplexer has two address inputs, nA0 and nA1. They also have an active LOW enable input (nE) and four mutually exclusive outputs which...