Nexperia B.V. Datasheets for Logic Decoders and Demultiplexers

Logic decoders and logic demultiplexers move data between inputs and outputs. In the case of digital decoders, the coded information is translated into familiar or uncoded formats, while digital multiplexers transmit data from one input through to several output lines. 
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Product Name Notes
The 74AHC138-Q100; 74AHCT138-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138-Q100;
The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138;
The 74AHC139-Q100; 74AHCT139-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC139-Q100;
The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC139;
The 74AHC1G66-Q100; 74AHCT1G66-Q100 is a single-pole, single-throw analog switch with two input/output terminals (nY and nZ) and a digital enable input (nE). When nE is LOW, the analog switch is...
The 74AUP1G18 is a 1-to-2 demultiplexer with a 3-state outputs. The device buffers the data on input A and passes it to output 1Y or 2Y, depending on whether the...
The 74AUP1G19 is a 1-to-2 decoder/demultiplexe r with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y...
The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output...
The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and...
The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and...
The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH...
The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH...
The 74HC154; 74HCT154 is a 4-to-16 line decoder/demultiplexe r. It decodes four binary weighted address inputs (A0 to A3) to sixteen mutually exclusive outputs (Y0 to Y15). The device features...
The 74HC1G66-Q100; 74HCT1G66-Q100 is a single-pole, single-throw analog switch with two input/output terminals (nY and nZ) and a digital enable input (nE). When nE is LOW, the analog switch is...
The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When...
The 74HC237-Q100 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237-Q100 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When...
The 74HC238-Q100; 74HCT238-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2...
The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2...
The 74HC42 is a one of ten BCD to decimal decoder. It accepts four BCD inputs (0A to 3A) and provides ten mutually exclusive outputs (0Y to 9Y). The logic...
The 74HC4511; 74HCT4511 is a BCD to 7-segment latch/decoder/driver with four address inputs (A, B, C, D), a latch enable input (LE), a ripple blanking input (BI), a lamp test...
The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexe r having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and...
The 74HC4851-Q100; 74HCT4851-Q100 are high-speed Si-gate CMOS devices and are specified in compliance with JEDEC standard no. 7A. The 74HC4851-Q100; 74HCT4851-Q100 are 8-channel analog multiplexers/demulti plexers with three digital select...
The 74LV138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (Y1, Y2 and E3).
The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3).
The 74LVC138A-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3).
The 74LVC139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all...
The 74LVC1G18 is a 1-to-2 demultiplexer with 3-state outputs. The device buffers the data on input A and passes it to output 1Y or 2Y, depending on whether the state...
The 74LVC1G18-Q100 is a 1-to-2 demultiplexer with 3-state outputs. The device buffers the data on input A and passes it to output 1Y or 2Y, depending on whether the state...
The 74LVC1G19 is a 1-of-2 decoder/demultiplexe r with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y...
The 74LVC1G19-Q100 is a 1-of-2 decoder/demultiplexe r with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y...
The CBT3245A-Q100 is an 8-pole, single-throw bus switch. The device features a single output enable input (OE) that controls eight switch channels. The switches are disabled when (OE) is HIGH.
The HEF4028B is a 4-bit BCD to 1-of-10 decoder. A 1-2-4-8 BCD code applied to inputs A0 to A3 causes the selected output to be HIGH, the other nine will...
The HEF4543B is a BCD to 7-segment latch/decoder/dr iver for liquid crystal and LED displays. It has four address inputs (D0 to D3), an active LOW latch enable input (LE),...
The HEF4555B contains two 1-of-4 decoders/demultiplex ers. Each has two address inputs (nA0 and nA1, an active LOW enable input (nE) and four mutually exclusive outputs which are active HIGH...
The HEF4555B-Q100 contains two 1-of-4 decoders/demultiplex ers. Each has two address inputs (nA0 and nA1, an active LOW enable input (nE) and four mutually exclusive outputs which are active HIGH...