Nexperia B.V. Low-power D-type flip-flop; positive-edge trigger 74AUP1G79GM,115

Description
The 74AUP1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-C (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Low-power D-type flip-flop; positive-edge trigger - 74AUP1G79GM,115 - Nexperia B.V.
Nijmegen, Netherlands
Low-power D-type flip-flop; positive-edge trigger
74AUP1G79GM,115
Low-power D-type flip-flop; positive-edge trigger 74AUP1G79GM,115
The 74AUP1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-C (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74AUP1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • CMOS low power dissipation
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-C (2.7 V to 3.6 V)
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Overvoltage tolerant inputs to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial power-down mode operation
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Logic - Flip Flops - 74AUP1G79GM,115 - Nova Technology(HK) Co.,Ltd
Futian District, Shenzhen, China
Logic - Flip Flops
74AUP1G79GM,115
Logic - Flip Flops 74AUP1G79GM,115
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Supplier's Site Datasheet
Flip Flops - 1727-74AUP1G79GM,115TR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Buy Now Datasheet
Flip Flops - 1727-74AUP1G79GM,115DKR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Buy Now Datasheet
Flip Flops - 1727-74AUP1G79GM,115CT-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Buy Now Datasheet
Yishun, Singapore
Logic - Logic - Flip Flops - 74AUP1G79GM,115
1007799-74AUP1G79GM,115
Logic - Logic - Flip Flops - 74AUP1G79GM,115 1007799-74AUP1G79GM,115
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1007799-74AUP1G79GM, 115 Packaging: Reel - TR Type: D-Type Mounting: SMD (SMT) Output Type: Non-Inverted Current - Output High, Low: 4mA, 4mA Number of Elements: 1 Number of Bits per Element: 1 Max Propagation Delay @ V, Max CL: 5.8ns @ 3.3V, 50pF Trigger Type: Positive Edge Current - Quiescent: 500nA Input Capacitance: 0.8pF Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 125°C (TA) Dimension: 6-XFDFN Purpose: Standard Supply Voltage - Operating: 0.8 V to 3.6 V Max Frequency: 309MHz Popularity: Medium Fake Threat In the Open Market: 45 pct. Supply and Demand Status: Sufficient

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1007799-74AUP1G79GM,115
Packaging: Reel - TR
Type: D-Type
Mounting: SMD (SMT)
Output Type: Non-Inverted
Current - Output High, Low: 4mA, 4mA
Number of Elements: 1
Number of Bits per Element: 1
Max Propagation Delay @ V, Max CL: 5.8ns @ 3.3V, 50pF
Trigger Type: Positive Edge
Current - Quiescent: 500nA
Input Capacitance: 0.8pF
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 125°C (TA)
Dimension: 6-XFDFN
Purpose: Standard
Supply Voltage - Operating: 0.8 V to 3.6 V
Max Frequency: 309MHz
Popularity: Medium
Fake Threat In the Open Market: 45 pct.
Supply and Demand Status: Sufficient

Buy Now Datasheet
Flip Flops - 74AUP1G79GM,115 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Buy Now Datasheet
 - 74AUP1G79GM,115 - Rochester Electronics
Newburyport, MA, United States
74AUP1G79GM - D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, XSON6

74AUP1G79GM - D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, XSON6

Supplier's Site Datasheet
Logic - Flip Flops - 74AUP1G79GM,115 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AUP1G79GM,115
Logic - Flip Flops 74AUP1G79GM,115
IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Nova Technology(HK) Co.,Ltd DigiKey Win Source Electronics Quarktwin Technology Ltd. Rochester Electronics Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AUP1G79GM,115 74AUP1G79GM,115 1727-74AUP1G79GM,115TR-ND 1007799-74AUP1G79GM,115 74AUP1G79GM,115 74AUP1G79GM,115 74AUP1G79GM,115
Product Name Low-power D-type flip-flop; positive-edge trigger Logic - Flip Flops Flip Flops Logic - Logic - Flip Flops - 74AUP1G79GM,115 Flip Flops Logic - Flip Flops
Flip-Flop Type D D D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered; Positive Edge Positive-edge Triggered
Supply Voltage 0.8 - 3.6 0.8V ~ 3.6V 0.8 V ~ 3.6 V 3.6V; 0.8V ~ 3.6V
Features ESD Protection
Propagation Delay 9.1 ns 5.8 ns 5.8 ns
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