Nexperia B.V. Octal D-type flip-flop; positive-edge trigger; 3-state 74ALVC374BQ,115

The 74ALVC374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops . This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.65 V to 3.6 V
• 3.6 V tolerant inputs/outputs
• CMOS low power consumption
• Direct interface with TTL levels (2.7 V to 3.6 V)
• Power-down mode
• Latch-up performance exceeds 250 mA
• Complies with JEDEC standards:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8B (2.7 V to 3.6 V)
• ESD protection:
• MM JESD22-A115-A exceeds 200 V
• HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
• CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1 kV
• ESD protection:
• HBM JESD22-A114E exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 °C to +85 °C

IC FF D-TYPE SNGL 8BIT 20DHVQFN

IC FF D-TYPE SNGL 8BIT 20DHVQFN

IC FF D-TYPE SNGL 8BIT 20DHVQFN

IC FF D-TYPE SNGL 8BIT 20DHVQFN