Nexperia B.V. Low-power dual D-type flip-flop; positive-edge trigger 74AUP2G79GT,115

Description
The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Product
Description
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Low-power dual D-type flip-flop; positive-edge trigger - 74AUP2G79GT,115 - Nexperia B.V.
Nijmegen, Netherlands
Low-power dual D-type flip-flop; positive-edge trigger
74AUP2G79GT,115
Low-power dual D-type flip-flop; positive-edge trigger 74AUP2G79GT,115
The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Logic - Flip Flops - 74AUP2G79GT,115 - Nova Technology(HK) Co.,Ltd
Futian District, Shenzhen, China
Logic - Flip Flops
74AUP2G79GT,115
Logic - Flip Flops 74AUP2G79GT,115
Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFDFN

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74AUP2G79GT,115 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74AUP2G79GT,115
Integrated Circuits (ICs) - Logic - Flip Flops 74AUP2G79GT,115
IC FF D-TYPE DUAL 1BIT 8XSON

IC FF D-TYPE DUAL 1BIT 8XSON

Supplier's Site
Flip Flops - 74AUP2G79GT,115 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFDFN

Buy Now Datasheet
Flip Flops - 1727-74AUP2G79GT,115DKR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFDFN

Buy Now Datasheet
Flip Flops - 1727-74AUP2G79GT,115TR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFDFN

Buy Now Datasheet
Flip Flops - 1727-74AUP2G79GT,115CT-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFDFN

Buy Now Datasheet
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia - 74AH2296 - Newark, An Avnet Company
Chicago, IL, United States
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia
74AH2296
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia 74AH2296
FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet
Logic - Flip Flops - 74AUP2G79GT,115 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AUP2G79GT,115
Logic - Flip Flops 74AUP2G79GT,115
IC FF D-TYPE DUAL 1BIT 8XSON

IC FF D-TYPE DUAL 1BIT 8XSON

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Nova Technology(HK) Co.,Ltd Shenzhen Shengyu Electronics Technology Limited Quarktwin Technology Ltd. DigiKey Newark, An Avnet Company Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AUP2G79GT,115 74AUP2G79GT,115 74AUP2G79GT,115 74AUP2G79GT,115 1727-74AUP2G79GT,115DKR-ND 74AH2296 74AUP2G79GT,115
Product Name Low-power dual D-type flip-flop; positive-edge trigger Logic - Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Flip Flops Flip Flops Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia Logic - Flip Flops
Flip-Flop Type D D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 0.8 - 3.6 3.6V; 0.8V ~ 3.6V 0.8V ~ 3.6V
Features ESD Protection
Propagation Delay 8.5 ns 5.8 ns
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