Nexperia B.V. Dual D-type flip-flop with set and reset; positive-edge trigger 74AHCT74PW,118

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Dual D-type flip-flop with set and reset; positive-edge trigger - 74AHCT74PW,118 - Nexperia B.V.
Nijmegen, Netherlands
Dual D-type flip-flop with set and reset; positive-edge trigger
74AHCT74PW,118
Dual D-type flip-flop with set and reset; positive-edge trigger 74AHCT74PW,118
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q). The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Features and benefits Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: For 74AHC74: CMOS level For 74AHCT74: TTL level ESD protection: HBM EIA/JESD22-A114E exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101C exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q).

The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features and benefits

  • Balanced propagation delays
  • All inputs have Schmitt-trigger actions
  • Inputs accept voltages higher than VCC
  • Input levels:
    • For 74AHC74: CMOS level
    • For 74AHCT74: TTL level
  • ESD protection:
    • HBM EIA/JESD22-A114E exceeds 2000 V
    • MM EIA/JESD22-A115-A exceeds 200 V
    • CDM EIA/JESD22-C101C exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 1727-8374-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-8374-6-ND
Flip Flops 1727-8374-6-ND
IC FF D-TYPE DUAL 1BIT 14TSSOP

IC FF D-TYPE DUAL 1BIT 14TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-8374-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-8374-1-ND
Flip Flops 1727-8374-1-ND
IC FF D-TYPE DUAL 1BIT 14TSSOP

IC FF D-TYPE DUAL 1BIT 14TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-8374-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-8374-2-ND
Flip Flops 1727-8374-2-ND
IC FF D-TYPE DUAL 1BIT 14TSSOP

IC FF D-TYPE DUAL 1BIT 14TSSOP

Supplier's Site Datasheet
Logic - Flip Flops - 74AHCT74PW,118 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AHCT74PW,118
Logic - Flip Flops 74AHCT74PW,118
IC FF D-TYPE DUAL 1BIT 14TSSOP

IC FF D-TYPE DUAL 1BIT 14TSSOP

Supplier's Site Datasheet
 - 74AHCT74PW,118 - Rochester Electronics
Newburyport, MA, United States
Nexperia 74AHCT74PW - D Flip-Flop, AHCT/VHCT/VT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, TSSOP14

Nexperia 74AHCT74PW - D Flip-Flop, AHCT/VHCT/VT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, TSSOP14

Supplier's Site Datasheet
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia - 74AH2172 - Newark, An Avnet Company
Chicago, IL, United States
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia
74AH2172
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia 74AH2172
FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Lingto Electronic Limited Rochester Electronics Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AHCT74PW,118 1727-8374-6-ND 74AHCT74PW,118 74AHCT74PW,118 74AH2172
Product Name Dual D-type flip-flop with set and reset; positive-edge trigger Flip Flops Logic - Flip Flops Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 5V; 4.5 - 5.5 4.5V ~ 5.5V
Features ESD Protection
Propagation Delay 3.3 ns 8.8 ns
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