Nexperia B.V. Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74DP-Q100H

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Single D-type flip-flop with set and reset; positive edge trigger - 74LVC1G74DP-Q100H - Nexperia B.V.
Nijmegen, Netherlands
Single D-type flip-flop with set and reset; positive edge trigger
74LVC1G74DP-Q100H
Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74DP-Q100H
The 74LVC1G74-Q100 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) Multiple package options

The 74LVC1G74-Q100 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 1.65 V to 5.5 V
  • Overvoltage tolerant inputs to 5.5 V
  • High noise immunity
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8-B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • MIL-STD-883, method 3015 exceeds 2000 V
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • Multiple package options
Supplier's Site Datasheet
Shenzhen, China
Logic - Flip Flops
74LVC1G74DP-Q100H
Logic - Flip Flops 74LVC1G74DP-Q100H
IC FF D-TYPE SNGL 1BIT 8TSSOP

IC FF D-TYPE SNGL 1BIT 8TSSOP

Supplier's Site Datasheet
 - 74LVC1G74DP-Q100H - Rochester Electronics
Newburyport, MA, United States
74LVC1G74 - Single D-type flip-flop with set and reset; positive edge trigger

74LVC1G74 - Single D-type flip-flop with set and reset; positive edge trigger

Supplier's Site Datasheet
Flip Flops - 1727-7463-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-7463-1-ND
Flip Flops 1727-7463-1-ND
IC FF D-TYPE SNGL 1BIT 8TSSOP

IC FF D-TYPE SNGL 1BIT 8TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-7463-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-7463-2-ND
Flip Flops 1727-7463-2-ND
IC FF D-TYPE SNGL 1BIT 8TSSOP

IC FF D-TYPE SNGL 1BIT 8TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-7463-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-7463-6-ND
Flip Flops 1727-7463-6-ND
IC FF D-TYPE SNGL 1BIT 8TSSOP

IC FF D-TYPE SNGL 1BIT 8TSSOP

Supplier's Site Datasheet
Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia - 74AH2537 - Newark, An Avnet Company
Chicago, IL, United States
Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia
74AH2537
Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia 74AH2537
FLIP FLOP, AEC-Q100, D, -40 TO 125DEG C ROHS COMPLIANT: YES

FLIP FLOP, AEC-Q100, D, -40 TO 125DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Lingto Electronic Limited Rochester Electronics DigiKey Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74LVC1G74DP-Q100H 74LVC1G74DP-Q100H 74LVC1G74DP-Q100H 1727-7463-1-ND 74AH2537
Product Name Single D-type flip-flop with set and reset; positive edge trigger Logic - Flip Flops Flip Flops Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia
Flip-Flop Type D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 5V; 1.65 - 5.5 1.65V ~ 5.5V
Features ESD Protection
Propagation Delay 3.5 ns 4.1 ns
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