Nexperia B.V. Low-power D-type flip-flop with set and reset; positive-edge trigger 74AUP1G74GN,115

The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 0.8 V to 3.6 V
• CMOS low power dissipation
• High noise immunity
• Overvoltage tolerant inputs to 3.6 V
• Low static power consumption; I_CC = 0.9 μA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Low noise overshoot and undershoot < 10 % of V_CC
• I_OFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V)
• JESD8-11 (0.9 V to 1.65 V)
• JESD8-7 (1.2 V to 1.95 V)
• JESD8-5 (1.8 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C

IC FF D-TYPE SNGL 1BIT 8XSON

74AUP1G74GN - D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO8

Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN