The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
Nexperia 74AUP1G74GN - D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO8
IC FF D-TYPE SNGL 1BIT 8XSON
IC FF D-TYPE SNGL 1BIT 8XSON
IC FF D-TYPE SNGL 1BIT 8XSON
IC FF D-TYPE SNGL 1BIT 8XSON
FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES
Nexperia B.V. | Rochester Electronics | Lingto Electronic Limited | DigiKey | Newark, An Avnet Company | |
---|---|---|---|---|---|
Product Category | Flip-Flops | Flip-Flops | Flip-Flops | Flip-Flops | Flip-Flops |
Product Number | 74AUP1G74GN,115 | 74AUP1G74GN,115 | 74AUP1G74GN,115 | 1727-6839-2-ND | 74AH2266 |
Product Name | Low-power D-type flip-flop with set and reset; positive-edge trigger | Logic - Flip Flops | Flip Flops | Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia | |
Flip-Flop Type | D | D | D | ||
Triggering | Positive-edge Triggered | Positive-edge Triggered | Positive-edge Triggered | ||
Supply Voltage | 0.8 - 3.6 | 0.8V ~ 3.6V | |||
Features | ESD Protection | ||||
Propagation Delay | 9.2 ns | 5.8 ns |